CN-117393009-B - Data receiving circuit, data receiving system and storage device

Abstract

The embodiment of the disclosure provides a data receiving circuit, a data receiving system and a storage device, wherein the data receiving circuit comprises a first amplifying module, a second amplifying module and a second amplifying module, wherein the first amplifying module comprises an amplifying unit, a first NMOS tube, a second NMOS tube and a third NMOS tube, the amplifying unit is provided with a first node, a second node, a third node and a fourth node, one end of the amplifying unit is connected with the first node, the other end of the amplifying unit is connected with one end of the second NMOS tube, the other end of the amplifying unit is connected with the second NMOS tube, the second NMOS tube is connected with the second node, the grid electrode of one of the first NMOS tube and the second NMOS tube receives a first complementary feedback signal, the grid electrode of the other one of the first NMOS tube and the second NMOS tube receives an enabling signal, one end of the third NMOS tube is connected with one end of the third NMOS tube, the other end of the third NMOS tube and the grid electrode of the fourth NMOS tube receives a second complementary feedback signal, and the grid electrode of the other one of the third NMOS tube and the fourth NMOS tube receives an enabling signal. The embodiment of the disclosure is at least beneficial to improving the processing speed of the data signal while improving the receiving performance of the data receiving circuit.

Inventors

• LIN FENG

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20220704

Claims (20)

1. 1. A data receiving circuit, comprising: A first amplifying module configured to receive an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal and a second reference signal, and to select, during the period when the enable signal has a first level value, the data signal to be compared with the first reference signal in a first manner and to output a first signal pair as a result of the first comparison in response to a sampling clock signal and based on the first feedback signal, or to select, during the period when the enable signal has a second level value, the data signal to be compared with the second reference signal in a second manner and to output a second signal pair as a result of the second comparison in response to the sampling clock signal, the first feedback signal being opposite in level to the second feedback signal, the first signal pair including a first signal and a second signal, the second signal pair including a third signal and a fourth signal; The first amplifying module comprises an amplifying unit, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first NMOS tube and a second NMOS tube, wherein the amplifying unit is provided with a first node, a second node, a third node and a fourth node, the first node outputs the first signal, the second node outputs the second signal, the third node outputs the third signal, the fourth node outputs the fourth signal, the first reference signal and the second reference signal are configured to be received, one end of the first NMOS tube is connected with the first node, the other end of the first NMOS tube is connected with one end of the second NMOS tube, the other end of the second NMOS tube is connected with the second node, the grid electrode of one of the first NMOS tube and the second NMOS tube receives a first complementary feedback signal, the grid electrode of the other one of the first NMOS tube receives the enabling signal, the first complementary feedback signal is opposite to the level of the first feedback signal, the third NMOS tube and the fourth NMOS tube is connected with the fourth NMOS tube, the other end of the fourth NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the other end of the fourth NMOS tube is connected with the fourth NMOS tube; and the second amplifying module is configured to receive the output signal of the first amplifying module as an input signal pair, amplify the voltage difference of the input signal pair and output a first output signal and a second output signal as the result of the amplifying process.
2. 2. The data receiving circuit of claim 1, wherein the first amplification module further comprises: The first node is connected with one end of the fifth NMOS tube, one end of the fifth NMOS tube is connected with one end of the sixth NMOS tube, the other end of the sixth NMOS tube is connected with the second node, the grid electrode of one of the fifth NMOS tube and the sixth NMOS tube receives the first complementary feedback signal, and the grid electrode of the other one of the fifth NMOS tube and the sixth NMOS tube receives the enabling signal.
3. 3. The data receiving circuit of claim 2, wherein a gate of the first NMOS transistor receives the enable signal, a gate of the second NMOS transistor receives the first complementary feedback signal, wherein a channel width of the first NMOS transistor is greater than a channel width of the second NMOS transistor, a gate of the fifth NMOS transistor receives the first complementary feedback signal, and a gate of the sixth NMOS transistor receives the enable signal, wherein a channel width of the fifth NMOS transistor is less than a channel width of the sixth NMOS transistor.
4. 4. The data receiving circuit of claim 2, wherein the fifth NMOS transistor has a channel width equal to the channel width of the second NMOS transistor, wherein the sixth NMOS transistor has a channel width equal to the channel width of the first NMOS transistor, and wherein the channel length of the first NMOS transistor, the channel length of the second NMOS transistor, the channel length of the fifth NMOS transistor, and the channel length of the sixth NMOS transistor are all equal.
5. 5. The data receiving circuit of claim 1, wherein the first amplification module further comprises: The system comprises a seventh NMOS tube and an eighth NMOS tube, wherein one end of the seventh NMOS tube is connected with the third node, the other end of the seventh NMOS tube is connected with one end of the eighth NMOS tube, the other end of the eighth NMOS tube is connected with the fourth node, the grid electrode of one of the seventh NMOS tube and the eighth NMOS tube receives the second complementary feedback signal, and the grid electrode of the other one of the seventh NMOS tube and the eighth NMOS tube receives the enabling signal.
6. 6. The data receiving circuit of claim 5, wherein a gate of the third NMOS transistor receives the enable signal, a gate of the fourth NMOS transistor receives the second complementary feedback signal, wherein a channel width of the third NMOS transistor is greater than a channel width of the fourth NMOS transistor, a gate of the seventh NMOS transistor receives the second complementary feedback signal, and a gate of the eighth NMOS transistor receives the enable signal, wherein a channel width of the seventh NMOS transistor is less than a channel width of the eighth NMOS transistor.
7. 7. The data receiving circuit of claim 5, wherein the seventh NMOS tube has a channel width equal to the channel width of the fourth NMOS tube, wherein the eighth NMOS tube has a channel width equal to the channel width of the third NMOS tube, and wherein the channel length of the third NMOS tube, the channel length of the fourth NMOS tube, the channel length of the seventh NMOS tube, and the channel length of the eighth NMOS tube are all equal.
8. 8. The data receiving circuit of claim 1, wherein the sampling clock signal comprises a first sampling clock signal and a second sampling clock signal, and wherein the amplifying unit comprises: A first comparison circuit having the first node and the second node, configured to receive the data signal and the first reference signal and to perform the first comparison in response to the first sampling clock signal; a clock generation circuit configured to receive the enable signal and an original sampling clock signal, and output the second sampling clock signal, wherein a phase of the second sampling clock signal is opposite to a phase of the original sampling clock signal during the enable signal has the first level value, and the second sampling clock signal is a logic high level signal during the enable signal has the second level value; And a second comparing circuit having the third node and the fourth node, configured to receive the data signal and the second reference signal and perform the second comparison in response to the second sampling clock signal during the enable signal having the first level value, and to conduct a connection path between the third node and a ground terminal and conduct a connection path between the fourth node and a ground terminal during the enable signal having the second level value.
9. 9. The data receiving circuit of claim 8, wherein the first comparison circuit comprises: a first current source configured to be connected between a power supply node and a fifth node, to provide a current to the fifth node in response to the first sampling clock signal; A first comparing unit connected to the first node, the second node, and the fifth node, configured to receive the data signal and the first reference signal, perform the first comparison when the first current source supplies a current to the fifth node, and output the first signal and the second signal; A first reset unit connected to the first node and the second node and configured to reset the first node and the second node in response to the first sampling clock signal; The second comparison circuit includes: a second current source configured to be connected between a power supply node and a sixth node, to supply a current to the sixth node in response to the second sampling clock signal; A second comparing unit connected to the third node, the fourth node, and the sixth node, configured to receive the data signal and the second reference signal, perform the second comparison when the second current source supplies a current to the sixth node, and output the third signal and the fourth signal; And a second reset unit connected between the third node and the fourth node and configured to reset the third node and the fourth node in response to the second sampling clock signal.
10. 10. The data receiving circuit of claim 9, wherein the first current source comprises: the first PMOS tube is connected between the power supply node and the fifth node, and the grid electrode of the first PMOS tube receives the first sampling clock signal; the second current source includes: and the second PMOS tube is connected between the power supply node and the sixth node, and the grid electrode of the second PMOS tube receives the second sampling clock signal.
11. 11. The data receiving circuit of claim 9, wherein the first comparing unit comprises: The third PMOS tube is connected between the first node and the fifth node, and the grid electrode of the third PMOS tube receives the data signal; The fourth PMOS tube is connected between the second node and the fifth node, and the grid electrode of the fourth PMOS tube receives the first reference signal; the second comparing unit includes: A fifth PMOS tube connected between the third node and the sixth node, wherein a grid electrode of the fifth PMOS tube receives the data signal; And the sixth PMOS tube is connected between the fourth node and the sixth node, and the grid electrode of the sixth PMOS tube receives the second reference signal.
12. 12. The data receiving circuit of claim 9, wherein the first reset unit comprises: A ninth NMOS tube connected between the first node and the ground terminal, and a grid electrode receiving the first sampling clock signal; A tenth NMOS tube connected between the second node and the ground terminal, and a grid electrode receiving the first sampling clock signal; the second reset unit includes: An eleventh NMOS tube connected between the third node and the ground terminal, and a grid electrode receiving the second sampling clock signal; and the twelfth NMOS tube is connected between the fourth node and the ground terminal, and the grid electrode receives the second sampling clock signal.
13. 13. The data receiving circuit of claim 8, wherein the clock generating circuit comprises: And one input end of the first NAND gate receives the original sampling clock signal, the other input end of the first NAND gate is connected with a power supply node, and the output end of the first NAND gate outputs the first sampling clock signal.
14. 14. The data receiving circuit of claim 8, wherein the clock generating circuit comprises: And one input end of the second NAND gate receives the original sampling clock signal, the other input end of the second NAND gate receives the enabling signal, and the output end of the second NAND gate outputs the second sampling clock signal.
15. 15. The data receiving circuit of claim 1, wherein the second amplification module comprises: A first input unit connecting a seventh node and an eighth node, configured to receive the first signal pair and perform a third comparison, and to provide signals to the seventh node and the eighth node, respectively, as a result of the third comparison; A second input unit connecting the seventh node and the eighth node, configured to receive the second signal pair and perform a fourth comparison, and to provide signals to the seventh node and the eighth node, respectively, as a result of the fourth comparison; And a latch unit connected to the seventh node and the eighth node, configured to amplify and latch a signal of the seventh node and a signal of the eighth node, and to output the first output signal and the second output signal through a first output node and a second output node, respectively.
16. 16. The data receiving circuit of claim 15, wherein the first input unit comprises: a thirteenth NMOS transistor having a drain connected to the seventh node, a source connected to a ground, and a gate receiving the first signal; a fourteenth NMOS tube, wherein the drain electrode of the fourteenth NMOS tube is connected with the eighth node, the source electrode of the fourteenth NMOS tube is connected with the ground terminal, and the grid electrode of the fourteenth NMOS tube receives the second signal; the second input unit includes: a fifteenth NMOS transistor having a drain connected to the seventh node, a source connected to a ground, and a gate receiving the third signal; And the drain electrode of the sixteenth NMOS tube is connected with the eighth node, the source electrode of the sixteenth NMOS tube is connected with the ground terminal, and the grid electrode of the sixteenth NMOS tube receives the fourth signal.
17. 17. The data receiving circuit of claim 15, wherein the latch unit comprises: A seventeenth NMOS transistor and a seventh PMOS transistor, wherein the gates of the seventeenth NMOS transistor and the seventh PMOS transistor are both connected to the second output node, the source of the seventeenth NMOS transistor is connected to the seventh node, the drain of the seventeenth NMOS transistor and the drain of the seventh PMOS transistor are both connected to the first output node, and the source of the seventh PMOS transistor is connected to the power supply node; The power supply comprises an eighteenth NMOS tube and an eighth PMOS tube, wherein the grid electrode of the eighteenth NMOS tube and the grid electrode of the eighth PMOS tube are both connected with the first output node, the source electrode of the eighteenth NMOS tube is connected with the eighth node, the drain electrode of the eighteenth NMOS tube and the drain electrode of the eighth PMOS tube are both connected with the second output node, and the source electrode of the eighth PMOS tube is connected with the power supply node.
18. 18. The data receiving circuit of claim 17, wherein the second amplification module further comprises: and the third reset unit is connected between the power supply node and the output end of the latch unit and is configured to reset the output end of the latch unit.
19. 19. The data receiving circuit of claim 18, wherein the third reset unit comprises: a ninth PMOS tube connected between the first output node and the power supply node, wherein a grid electrode of the ninth PMOS tube receives an original sampling clock signal; And a tenth PMOS tube connected between the second output node and the power supply node, wherein a grid electrode of the tenth PMOS tube receives the original sampling clock signal.
20. 20. The data receiving circuit of claim 1, further comprising: A first inverting circuit configured to receive the first feedback signal and output the first complementary feedback signal; a second inverting circuit configured to receive the second feedback signal and output the second complementary feedback signal.

Description

Data receiving circuit, data receiving system and storage device Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a data receiving circuit, a data receiving system and a storage device. Background In memory applications, as the signal transmission rate is faster and faster, the influence of channel loss on signal quality is greater and greater, which is easy to cause intersymbol interference, and in addition, the difference of level values between a data signal received by a data receiving circuit in a memory and a reference signal may affect the judgment of the data receiving circuit on the data signal, thereby affecting the accuracy of a signal output by the data receiving circuit. The channel is usually compensated by an Equalizer circuit, which may be a CTLE (Continuous TIME LINEAR Equalizer) or a DFE (Decision Feedback Equalizer ). However, the accuracy of the signal output by the equalizing circuit adopted at present needs to be improved, the receiving performance of the equalizing circuit needs to be improved, and the processing speed of the equalizing circuit on the data signal needs to be improved. Disclosure of Invention The embodiment of the disclosure provides a data receiving circuit, a data receiving system and a storage device, which are at least beneficial to improving the processing speed of a data signal while improving the receiving performance of the data receiving circuit. According to some embodiments of the present disclosure, there is provided in one aspect a data receiving circuit comprising a first amplifying module configured to receive an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal and a second reference signal, during which the enable signal has a first level value, in response to a sampling clock signal and based on the first feedback signal, to select the data signal to be first compared with the first reference signal and output a first pair of signals as a result of the first comparison, or in response to the sampling clock signal and based on the second feedback signal, to select the data signal to be second compared with the second reference signal and output a second pair of signals as a result of the second comparison, during which the enable signal has a second level value, to respond to the sampling clock signal, to make the first comparison and output the first pair of signals, the first feedback signal being opposite to the level of the second feedback signal, the first feedback signal including a first signal and a second signal, the second signal including a third signal and a fourth node, to be amplified, and a fourth node to be connected, the second NMOS transistor is connected with one end of the second NMOS transistor, the other end of the second NMOS transistor is connected with the second node, the grid electrode of one of the first NMOS transistor and the second NMOS transistor receives a first complementary feedback signal, the grid electrode of the other one of the first NMOS transistor and the second NMOS transistor receives the enabling signal, the first complementary feedback signal is opposite to the first feedback signal in level, the third NMOS transistor and the fourth NMOS transistor are connected with one end of the third NMOS transistor, the other end of the third NMOS transistor is connected with one end of the fourth NMOS transistor, the other grid electrode of the third NMOS transistor and the fourth NMOS transistor receives a second complementary feedback signal, the grid electrode of the other one of the third NMOS transistor and the fourth NMOS transistor receives the enabling signal, the second complementary feedback signal is opposite to the second feedback signal in level, and the second amplifying module is configured to receive an output signal of the first amplifying module as an input signal pair, process the input signal pair, output the first amplifying signal and the second amplifying result as an output voltage difference. In some embodiments, the first amplifying module further comprises a fifth NMOS tube and a sixth NMOS tube, wherein one end of the fifth NMOS tube is connected with the first node, the other end of the fifth NMOS tube is connected with one end of the sixth NMOS tube, the other end of the sixth NMOS tube is connected with the second node, the grid electrode of one of the fifth NMOS tube and the sixth NMOS tube receives the first complementary feedback signal, and the grid electrode of the other one of the fifth NMOS tube and the sixth NMOS tube receives the enabling signal. In some embodiments, the gate of the first NMOS receives the enable signal, the gate of the second NMOS receives the first complementary feedback signal, wherein the channel width of the first NMOS is greater than the channel width of the second NMOS, the gate of the fifth NMOS receives the first complementary feedb