CN-117413310-B - Shift register, gate driving circuit and display device

Abstract

A shift register, a gate driving circuit and a display device includes an INPUT circuit (1) configured to control writing of a signal supplied from a signal INPUT terminal (INPUT) to a third node (N3) in response to a signal supplied from a first clock signal terminal (CK), a first control circuit (2) configured to control writing of a voltage supplied from the first power supply terminal to a first node (N1) in response to a signal supplied from a preset control signal terminal (CS) and a signal supplied from a second clock signal terminal (CKB), a second control circuit (3) configured to control writing of a voltage supplied from the second power supply terminal to the first node (N1) in response to a signal supplied from the signal INPUT terminal (INPUT), an output circuit (4) configured to write a voltage supplied from the second power supply terminal to a signal output terminal (OUT) in response to a control of a voltage at a fourth node (N4), and the third node (N3) and the fourth node (N4) are coupled.

Inventors

• WEI LIHENG
• YANG HUIJUAN
• LIU TINGLIANG
• ZHANG YI
• SHU XIAOQING
• LI LINGTONG
• LIAO MAOYING
• CHEN TIANCI

Assignees

• 京东方科技集团股份有限公司
• 成都京东方光电科技有限公司

Dates

Publication Date

20260512

Application Date

20220324

Claims (13)

1. 1. A shift register, comprising: an input circuit coupled to a signal input terminal, a first clock signal terminal, and a third node, configured to control writing of a signal provided by the signal input terminal to the third node in response to a signal provided by the first clock signal terminal; the first control circuit is coupled with a first power supply end, a preset control signal end, a second clock signal end and a first node and is configured to control writing of voltage provided by the first power supply end into the first node in response to signals provided by the preset control signal end and signals provided by the second clock signal end; A second control circuit coupled to a second power supply terminal, the signal input terminal, and the first node, and configured to control writing of a voltage provided by the second power supply terminal to the first node in response to a signal provided by the signal input terminal; An output circuit coupled to a signal output terminal, the first power terminal, the second power terminal, the first node, and a fourth node, configured to write a voltage provided by the second power terminal to the signal output terminal in response to control of a voltage at the first node, and write a voltage provided by the first power terminal to the signal output terminal in response to control of a voltage at the fourth node, the third node being coupled to the fourth node; A sixth transistor located between the third node and the fourth node, the third node being coupled to the fourth node through the sixth transistor; the control electrode of the sixth transistor is coupled to the first power supply terminal, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the fourth node.
2. 2. The shift register of claim 1, wherein the first control circuit comprises a first transistor and a second transistor; the control electrode of the first transistor is coupled with the preset control signal end, the first electrode of the first transistor is coupled with the first power end, and the second electrode of the first transistor is coupled with the first electrode of the second transistor; The control electrode of the second transistor is coupled with a second clock signal end, and the second electrode of the second transistor is coupled with the first node.
3. 3. The shift register of claim 1, wherein the first control circuit comprises a first transistor and a second transistor; the control electrode of the first transistor is coupled with the preset control signal end, the first electrode of the first transistor is coupled with the second electrode of the second transistor, and the second electrode of the first transistor is coupled with the first node; The control electrode of the second transistor is coupled with a second clock signal end, and the first electrode of the second transistor is coupled with the first power end.
4. 4. A shift register according to claim 2 or 3, wherein the first transistor is an N-type transistor and the other transistors in the shift register than the first transistor are P-type transistors.
5. 5. The shift register of claim 4, wherein the first transistor is a metal oxide transistor, and the other transistors in the shift register except for the first transistor are all low temperature polysilicon type transistors.
6. 6. The shift register of claim 1, wherein the second control circuit comprises a third transistor; the control electrode of the third transistor is coupled to the signal input terminal, the first electrode of the third transistor is coupled to the second power supply terminal, and the second electrode of the third transistor is coupled to the first node.
7. 7. The shift register of claim 1, wherein the input circuit comprises a fourth transistor; The control electrode of the fourth transistor is coupled to the first clock signal terminal, the first electrode of the fourth transistor is coupled to the signal input terminal, and the second electrode of the fourth transistor is coupled to the third node.
8. 8. The shift register according to claim 1, wherein the output circuit includes a seventh transistor and an eighth transistor; a control electrode of the seventh transistor is coupled with the fourth node, a first electrode of the seventh transistor is coupled with the first power supply end, and a second electrode of the seventh transistor is coupled with the signal output end; The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the signal output terminal, and the second electrode of the eighth transistor is coupled to the second power supply terminal.
9. 9. The shift register of claim 1, further comprising a noise reduction circuit coupled to the second power supply terminal, the first node, and the third node, configured to write a voltage provided by the second power supply terminal to the third node in response to control of the voltage at the first node.
10. 10. The shift register of claim 9, wherein the noise reduction circuit comprises a fifth transistor; the control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the second power supply terminal.
11. 11. The shift register of claim 1, further comprising a second capacitor; the first end of the second capacitor is coupled with the first node, and the second end of the second capacitor is coupled with the first power end or the second power end.
12. 12. A gate driving circuit comprising a plurality of shift registers in cascade, the shift registers employing the shift register according to any one of claims 1to 11; The signal input end of the shift register positioned at the first stage is coupled with the frame start signal end; and the signal input end of any one stage of shift register except the first stage is coupled with the signal output end of the shift register of the previous stage.
13. 13. A display device comprising the gate driving circuit as claimed in claim 12.

Description

Shift register, gate driving circuit and display device Technical Field The present invention relates to the field of display, and in particular, to a shift register, a gate driving circuit, and a display device. Background With the development of display technology, a light-emitting control transistor for controlling whether a driving transistor outputs a driving current is generally disposed in a pixel driving circuit, and the light-emitting control transistor is generally controlled by a light-emitting control signal line. For the emission control signal line, a corresponding emission control gate drive circuit needs to be arranged. In the prior art, a transistor in a grid driving circuit for light emission control is integrated on an Array substrate by adopting an Array substrate row driving (GATE DRIVER on Array, abbreviated as GOA) technology and is used for scanning and driving a light emission control signal line in a display panel, so that a part of a grid driving IC (integrated circuit) can be omitted, and the realization of a narrow frame is facilitated. However, in practical use, it has been found that the conventional gate driving circuit for controlling light emission has a complicated circuit configuration and occupies a large space. Disclosure of Invention The invention aims to at least solve one of the technical problems in the prior art, and provides a shift register, a gate driving circuit and a display device. In a first aspect, an embodiment of the present disclosure provides a shift register, including: an input circuit coupled to a signal input terminal, a first clock signal terminal, and a third node, configured to control writing of a signal provided by the signal input terminal to the third node in response to a signal provided by the first clock signal terminal; The first control circuit is coupled with a first power supply end, a preset control signal end, a second clock signal end and a first node and is configured to respond to signals provided by the preset control signal end and signals provided by the second clock signal end to control writing of voltage provided by the first power supply end into the first node; A second control circuit coupled to a second power supply terminal, the signal input terminal, and the first node, and configured to control writing of a voltage provided by the second power supply terminal to the first node in response to a signal provided by the signal input terminal; and an output circuit coupled to the signal output terminal, the first power terminal, the second power terminal, the first node, and the fourth node, configured to write a voltage provided by the second power terminal to the signal output terminal in response to control of a voltage at the first node, and write a voltage provided by the first power terminal to the signal output terminal in response to control of a voltage at the fourth node, the third node being coupled to the fourth node. In some embodiments, the first control circuit includes a first transistor and a second transistor; the control electrode of the first transistor is coupled with the preset control signal end, the first electrode of the first transistor is coupled with the first power end, and the second electrode of the first transistor is coupled with the first electrode of the second transistor; The control electrode of the second transistor is coupled with a second clock signal end, and the second electrode of the second transistor is coupled with the first node. In some embodiments, the first control circuit includes a first transistor and a second transistor; the control electrode of the first transistor is coupled with the preset control signal end, the first electrode of the first transistor is coupled with the second electrode of the second transistor, and the second electrode of the first transistor is coupled with the first node; The control electrode of the second transistor is coupled with a second clock signal end, and the first electrode of the second transistor is coupled with the first power end. In some embodiments, the preset control signal terminal is the third node. In some embodiments, the preset control signal terminal is the signal input terminal. In some embodiments, the first transistor is an N-type transistor, and the other transistors in the shift register except for the first transistor are P-type transistors. In some embodiments, the first transistor is a metal oxide type transistor, and the other transistors in the shift register except for the first transistor are all low temperature polysilicon type transistors. In some embodiments, the second control circuit includes a third transistor; the control electrode of the third transistor is coupled to the signal input terminal, the first electrode of the third transistor is coupled to the second power supply terminal, and the second electrode of the third transistor is coupled to the first node. In some embodiments, the input circuit in