CN-117456874-B - Gate driving circuit and display panel

Abstract

The grid driving circuit comprises a grid driving unit which is arranged in a multistage cascade mode, wherein the grid driving unit comprises a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module and a pull-down maintenance module, the pull-up control module is used for controlling the potential of a pull-down Gao Shang pull-down node under the control of a first clock signal input end, the pull-down control module is used for controlling the potential of a pull-down Gao Xia pull-down node under the control of the first clock signal, the first pull-down module is used for pulling down the potential of the pull-down node to the potential of the first clock signal under the control of the potential of the pull-up node, and the pull-down maintenance module is used for keeping the potential of the pull-up node at a low potential under the control of the second clock signal input by the second clock signal input end and the potential of the pull-down node.

Inventors

• ZHOU XIANG
• HAN BAIXIANG
• LI GUANGYAO

Assignees

• 深圳市华星光电半导体显示技术有限公司

Dates

Publication Date

20260512

Application Date

20231024

Claims (10)

1. 1. The grid driving circuit is characterized by comprising a grid driving unit which is arranged in a multistage cascade manner, wherein the grid driving unit comprises a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module and a pull-down maintenance module; The pull-up control module is electrically connected with the first clock signal input end and the pull-up node, and is used for pulling down the potential of the pull-up node under the control of the first clock signal input by the first clock signal input end; The first output module is electrically connected with the second clock signal input end, the pull-up node and the current stage scanning signal output end, and is used for outputting the current stage scanning signal under the control of the potential of the pull-up node; The second output module is electrically connected with a third clock signal input end, the pull-up node and the current-stage transmission signal output end, and is used for outputting the current-stage transmission signal under the control of the potential of the pull-up node; The pull-down control module is electrically connected with the first clock signal input end and the pull-down node, and is used for pulling down the potential of the pull-down node under the control of the first clock signal; The first pull-down module is electrically connected with the first clock signal input end, the pull-up node and the pull-down node, and is used for pulling down the potential of the pull-down node to the potential of the first clock signal under the control of the potential of the pull-up node; The second pull-down module is electrically connected with the current-stage scanning signal output end, the current-stage transmission signal output end and the pull-down node, and is used for pulling down the potential of the current-stage scanning signal and the potential of the current-stage transmission signal under the control of the potential of the pull-down node; The pull-down maintaining module is electrically connected with the second clock signal input end, the pull-up node and the pull-down node, and is used for keeping the potential of the pull-up node at a low potential under the control of the second clock signal input by the second clock signal input end and the potential of the pull-down node.
2. 2. The gate driving circuit according to claim 1, wherein a phase of the first clock signal is opposite to a phase of the second clock signal, and a phase of the second clock signal is identical to a phase of a third clock signal input to the third clock signal input terminal.
3. 3. The gate drive circuit of claim 1 or 2, wherein the pull-up control module comprises a first transistor having a gate electrically connected to a first clock signal input, a first electrode electrically connected to a superior signaling signal input, and a second electrode electrically connected to the pull-up node.
4. 4. The gate driving circuit according to claim 1 or 2, wherein the first output module includes a second transistor and a first capacitor, a gate of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to a second clock signal input terminal, and a second electrode of the second transistor is electrically connected to the current stage scanning signal output terminal; A first polar plate of the first capacitor is electrically connected with the pull-up node, and a second polar plate of the first capacitor is electrically connected with the current stage scanning signal output end; the second output module comprises a third transistor, wherein the grid electrode of the third transistor is electrically connected with the pull-up node, the first electrode of the third transistor is electrically connected with the third clock signal input end, and the second electrode of the third transistor is electrically connected with the current-stage signal output end.
5. 5. The gate driving circuit according to claim 1 or 2, wherein the pull-down control module comprises a fourth transistor, a gate of the fourth transistor is electrically connected to the first clock signal input terminal, a first electrode of the fourth transistor is electrically connected to the reference high level signal input terminal, and a second electrode of the fourth transistor is electrically connected to the pull-down node.
6. 6. The gate driving circuit according to claim 1 or 2, wherein the first pull-down module includes a fifth transistor, a gate of the fifth transistor is electrically connected to the pull-up node, a first electrode of the fifth transistor is electrically connected to a first clock signal input terminal, and a second electrode of the fifth transistor is electrically connected to the pull-down node; the second pull-down module comprises a sixth transistor, a seventh transistor and a second capacitor, wherein the grid electrode of the sixth transistor is electrically connected with the pull-down node, the first electrode of the sixth transistor is electrically connected with the reference low-level signal input end, and the second electrode of the sixth transistor is electrically connected with the current-stage scanning signal output end; The grid electrode of the seventh transistor is electrically connected with the pull-down node, the first electrode of the seventh transistor is electrically connected with the reference low-level signal input end, and the second electrode of the seventh transistor is electrically connected with the current-stage signaling output end; the first polar plate of the second capacitor is electrically connected with the pull-down node, and the second polar plate of the second capacitor is electrically connected with the reference low-level signal input end.
7. 7. The gate driving circuit according to claim 1 or 2, wherein the pull-down maintaining module includes an eighth transistor having a gate electrically connected to the pull-down node, a first electrode electrically connected to a reference low level signal input terminal, and a ninth transistor having a second electrode electrically connected to a first electrode; The gate of the ninth transistor is electrically connected to the second clock signal input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node.
8. 8. The gate driving circuit according to claim 1 or 2, wherein the gate driving unit further comprises a detection module electrically connected to the pull-up node, the detection module being configured to pull up a potential of the pull-up node in at least one stage of the gate driving units after the gate driving units of the multi-stage cascade each output the current stage scanning signal; And the current stage scanning signal output end outputs a current stage scanning compensation signal under the control of the potential of the pull-up node.
9. 9. The gate driving circuit of claim 8, wherein the detection module comprises a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor, the gate of the tenth transistor being electrically connected to the selection signal input terminal, the first electrode of the tenth transistor being electrically connected to the upper level signal input terminal, the second electrode of the tenth transistor being electrically connected to the gate of the eleventh transistor; a first electrode of the eleventh transistor is electrically connected to the reference high-level signal input terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor; the gate of the twelfth transistor is electrically connected to the reset signal input terminal, and the second electrode of the twelfth transistor is electrically connected to the pull-up node; The first plate of the third capacitor is electrically connected to the gate of the eleventh transistor, and the second plate of the third capacitor is electrically connected to the first electrode of the eleventh transistor.
10. 10. A display panel comprising a pixel cell and a gate drive circuit according to any one of claims 1 to 9, the gate drive circuit being electrically connected to the pixel cell.

Description

Gate driving circuit and display panel Technical Field The application relates to the technical field of display, in particular to a gate driving circuit and a display panel. Background The Gate-driver On Array (GOA) technology is to manufacture a Gate driving circuit On a thin film transistor Array substrate by using a thin film transistor Array (Array) process to realize a progressive scanning driving mode. The gate driving circuit includes a plurality of cascaded gate driving units. In order to ensure the basic function of the gate driving circuit and improve the stability of the gate driving circuit, tens of thin film transistors are generally arranged in the existing gate driving unit, and are respectively electrically connected with a plurality of different driving signal input ends, so that the structure of the gate driving circuit is very complex. Disclosure of Invention An object of the embodiments of the present application is to provide a gate driving circuit and a display panel, which can reduce the number of driving signal input terminals to be connected to a gate driving unit, thereby simplifying the structure of the gate driving circuit and the display panel. In one aspect, the embodiment of the application provides a gate driving circuit, which comprises a gate driving unit in multistage cascade arrangement, wherein the gate driving unit comprises a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module and a pull-down maintenance module; the pull-up control module is electrically connected with a first clock signal input end and the pull-up node and is used for pulling down the potential of the pull-up node under the control of a first clock signal input by the first clock signal input end, the first output module is electrically connected with a second clock signal input end, the pull-up node and a current level scanning signal output end and is used for outputting a current level scanning signal under the control of the potential of the pull-up node, the second output module is electrically connected with a third clock signal input end, the pull-up node and a current level signal output end and is used for outputting a current level signal under the control of the potential of the pull-up node, the pull-down control module is electrically connected with the first clock signal input end and the pull-down node and is used for pulling down the potential of the pull-down node under the control of the first clock signal, the first pull-down module is electrically connected with the first clock signal input end, the pull-up node and the current level scanning signal output end, the second output module is electrically connected with the first clock signal input end, the pull-down node and the current level scanning signal output end, and the pull-down module is electrically connected with the first clock signal input end and the pull-down node, the second pull-down module is used for pulling down the potential of the current level scanning signal and the potential of the current level transmission signal under the control of the potential of the pull-down node, the pull-down maintaining module is electrically connected with the second clock signal input end, the pull-up node and the pull-down node, and the pull-down maintaining module is used for keeping the potential of the pull-up node at a low potential under the control of the second clock signal input end and the potential of the pull-down node. Optionally, in some embodiments of the present application, a phase of the first clock signal is opposite to a phase of the second clock signal, and a phase of the second clock signal is the same as a phase of a third clock signal input to the third clock signal input. Optionally, in some embodiments of the present application, the pull-up control module includes a first transistor, a gate of the first transistor is electrically connected to a first clock signal input terminal, a first electrode of the first transistor is electrically connected to a previous stage signal input terminal, and a second electrode of the first transistor is electrically connected to the pull-up node. Optionally, in some embodiments of the present application, the first output module includes a second transistor and a first capacitor, a gate of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the second clock signal input terminal, a second electrode of the second transistor is electrically connected to the current stage scan signal output terminal, a first plate of the first capacitor is electrically connected to the pull-up node, a second plate of the first capacitor is electrically connected to the current stage scan signal output terminal, the second output module includes a third transistor, a gate