CN-117474058-B - Computing circuit

CN117474058BCN 117474058 BCN117474058 BCN 117474058BCN-117474058-B

Abstract

The present application relates to a calculation circuit. The computing circuit comprises a plurality of computing units which are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, the multiplication computing circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, the precharge circuit and the computing result output circuit are electrically connected with a computing output node between the first ferroelectric transistor and the second ferroelectric transistor, the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the driving of a writing voltage, the precharge circuit is used for adjusting the computing output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistance state, the first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the computing output node is adjusted to the target voltage, and the computing result output circuit is used for outputting the voltage of the computing output node after receiving the signal input voltage. By adopting the computing circuit provided by the application, the integration level can be improved, and the power consumption can be reduced.

Inventors

REN TIANLING
WANG ZHENZE
YAN ANZHI
YAN ZHAOYI
LIU HOUFANG
YANG DIE

Assignees

清华大学

Dates

Publication Date: 20260512
Application Date: 20230927

Claims (10)

1. The computing circuit is characterized by comprising a plurality of computing units which are arranged in an array, wherein each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, the multiplication computing circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the computing result output circuit are electrically connected with a computing output node between the first ferroelectric transistor and the second ferroelectric transistor; The first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent the weight value of the neural network unit corresponding to the computing unit; The precharge circuit is used for adjusting the calculation output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistance state; The first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage; The calculation result output circuit is used for outputting the voltage of the calculation output node after receiving the signal input voltage so as to obtain a calculation result of the multiplication calculation circuit based on the signal input voltage and the weight value; The first ferroelectric transistor is in a low-resistance state, the second ferroelectric transistor is in a high-resistance state, and the weight value used for representing the neural network unit corresponding to the corresponding calculation unit is 1; The first ferroelectric transistor is in a high-resistance state, the second ferroelectric transistor is in a low-resistance state, and the weight value used for representing the neural network unit corresponding to the corresponding calculation unit is-1; The first ferroelectric transistor and the second ferroelectric transistor are in a high-resistance state, and the weight value used for representing the neural network unit corresponding to the corresponding computing unit is 0.
2. The computing circuit of claim 1, wherein a first pole of the first ferroelectric transistor is connected to a first pole of the second ferroelectric transistor, a second pole of the first ferroelectric transistor is a first signal input node, a second pole of the second ferroelectric transistor is a second signal input node, a gate of the first ferroelectric transistor is a first write voltage drive node, and a gate of the second ferroelectric transistor is a second write voltage drive node; the first signal input node and the second signal input node are used for inputting the signal input voltage; The first write voltage driving node and the second write voltage driving node are used for inputting the write voltage.
3. The computing circuit of claim 2, wherein the computation output node is located between a first pole of the first ferroelectric transistor and a first pole of the second ferroelectric transistor.
4. A computing circuit according to any one of claims 1 to 3, wherein the precharge circuit comprises a first transistor having a source connected to a first voltage source for outputting the target voltage, a drain connected to the computing output node, and a gate for receiving a pulse signal to adjust the computing output node to the target voltage based on the pulse signal.
5. The computing circuit of claim 4, further comprising a word line WL; a gate of a first transistor in a precharge circuit in each of the calculation units is connected to the WL; the WL is configured to output the pulse signal to a gate of a first transistor in a precharge circuit in each of the computing units.
6. A calculation circuit according to any one of claims 1 to 3, further comprising a bit line RBL, wherein a calculation result output circuit in each of the calculation units is connected to the RBL to output a calculation result to the RBL.
7. The computing circuit of claim 6, wherein the computation result output circuit comprises a first capacitance for coupling a voltage of the computation output node to the RBL.
8. The computing circuit of claim 7, wherein a second transistor is provided on the RBL for performing discharge processing and floating processing on the RBL before the multiplication computing circuit performs computation based on the signal input voltage and the weight value.
9. The computing circuit of claim 6, wherein the computation result output circuit comprises a third transistor and a fourth transistor, the bit line RBL comprising a first RBL and a second RBL, gates of the third transistor and the fourth transistor each being coupled to the computation output node, a source of the third transistor being coupled to a second voltage source, a source of the fourth transistor being coupled to the second RBL, a drain of the third transistor being coupled to the first RBL, a drain of the fourth transistor being coupled to ground; the third transistor and the fourth transistor are configured to perform a charging operation or a discharging operation on the first RBL and the second RBL, respectively, under control of the calculated output node voltage.
10. The computing circuit of claim 9, wherein the first RBL and the second RBL are connected by a computation result processing circuit, the computation result processing circuit including a first switch, a second switch, a third switch, a fourth switch, a second capacitor, and a third capacitor; The calculation result processing circuit is used for carrying out accumulation processing on the voltages of the first RBL and the second RBL so as to obtain calculation results of a plurality of calculation units.

Description

Computing circuit Technical Field The application relates to the technical field of circuits, in particular to a computing circuit. Background With the rapid development of deep neural network technology, the operation requirement and the storage requirement of the deep neural network (Deep Neural Networks, DNN) are higher and higher, and meanwhile, the power consumption of the device is required to be controlled so as to improve the DNN reasoning efficiency. In the prior art, when improving the DNN reasoning efficiency, a TNN array unit is generally designed based on a three-value neural network (Ternary Neural Network, TNN), and the reasoning precision and the reasoning speed of DNN are balanced by using a weight value and excitation with lower precision, so that the cost of a small amount of reasoning precision is reduced, the DNN reasoning speed is improved, and the DNN reasoning efficiency is further improved. However, the existing TNN array unit uses more components and has larger area, so that the TNN array unit has lower integration level and larger power consumption. Disclosure of Invention In view of the above, it is necessary to provide a computing circuit with high integration and low power consumption. The application provides a calculation circuit, which comprises a plurality of calculation units arranged in an array, wherein each calculation unit comprises a multiplication calculation circuit, a precharge circuit and a calculation result output circuit, the multiplication calculation circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are mutually connected, the precharge circuit and the calculation result output circuit are electrically connected with calculation output nodes between the first ferroelectric transistor and the second ferroelectric transistor, the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the driving of write voltage so as to represent the weight value of a neural network unit corresponding to the calculation unit, the precharge circuit is used for adjusting the calculation output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistance state, the first ferroelectric transistor and the second ferroelectric transistor are used for receiving signal input voltage after the calculation output node is adjusted to the target voltage, and the calculation result output circuit is used for carrying out the voltage multiplication calculation output on the calculation output node to obtain the calculation result based on the signal input voltage after the signal input voltage is received. In one embodiment, the first electrode of the first ferroelectric transistor is connected to the first electrode of the second ferroelectric transistor, the second electrode of the first ferroelectric transistor is a first signal input node, the second electrode of the second ferroelectric transistor is a second signal input node, the gate of the first ferroelectric transistor is a first write voltage driving node, the gate of the second ferroelectric transistor is a second write voltage driving node, the first signal input node and the second signal input node are used for inputting the signal input voltage, and the first write voltage driving node and the second write voltage driving node are used for inputting the write voltage. In one embodiment, the compute output node is located between the first pole of the first ferroelectric transistor and the first pole of the second ferroelectric transistor. In one embodiment, the precharge circuit includes a first transistor having a source connected to a first voltage source for outputting the target voltage, a drain connected to the calculation output node, and a gate for receiving a pulse signal to adjust the calculation output node to the target voltage based on the pulse signal. In one embodiment, the computing circuit further comprises a word line WL, gates of the first transistors in the precharge circuits in the computing units are connected with the WL, and the WL is used for outputting the pulse signals to the gates of the first transistors in the precharge circuits in the computing units. In one embodiment, the computing circuit further includes a bit line RBL, and the computing result output circuit in each computing unit is connected to the RBL to output the computing result to the RBL. In one embodiment, the calculation result output circuit includes a first capacitor for coupling the voltage of the calculation output node to the RBL. In one embodiment, the RBL is provided with a second transistor for performing a discharging process and a floating process on the RBL before the multiplication calculating circuit calculates based on the signal input voltage and the weight value. In one embodiment, the calculation result output circuit comprises a