CN-117474059-B - Computing circuit

CN117474059BCN 117474059 BCN117474059 BCN 117474059BCN-117474059-B

Abstract

The present application relates to a calculation circuit. The computing unit comprises a multiplication computing circuit, a pre-charging circuit and a computing result output circuit, wherein the computing result output circuits of the computing units of different types are different, the computing result output circuit is used for respectively outputting the voltage of a computing output node through N output channels after receiving signal input voltage so as to obtain a first computing result obtained by the multiplication computing circuit through N times of coupling of the voltage of the computing output node, the first computing result is obtained by computing according to the signal input voltage and a first neural network weight value, the first neural network weight value is obtained according to an initial neural network weight value and a coupling frequency N, and the coupling frequency N corresponding to the computing result output circuit in the computing units of different types is different. The calculation circuit provided by the application reduces the power consumption, improves the integration level and simultaneously realizes the calculation of the multi-valued neural network.

Inventors

REN TIANLING
WANG ZHENZE
YAN ANZHI
YAN ZHAOYI
LIU HOUFANG
YANG DIE

Assignees

清华大学

Dates

Publication Date: 20260512
Application Date: 20230927

Claims (13)

1. The computing circuit is characterized by comprising a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the computing units of different types are different; the multiplication calculating circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the calculation result output circuit are electrically connected with a calculation output node between the first ferroelectric transistor and the second ferroelectric transistor; The first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value; the precharge circuit is used for adjusting the calculation output node to a target voltage; The first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage; The calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input voltage so as to obtain a first calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the first calculation result is calculated according to the signal input voltage and a first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the coupling times N, N is a positive integer, and the coupling times N corresponding to the calculation result output circuit in the calculation units of different types are different.
2. The computing circuit of claim 1, wherein the computation result output circuit comprises N sub-output circuits, wherein each of the sub-output circuits is configured to output the voltage of the computation output node through a different output path.
3. The computing circuit of claim 2, wherein the sub-output circuit comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are both connected to the computing output node, the first pole of the first transistor is connected to a first voltage source, and the first pole of the second transistor is grounded.
4. The computing circuit of claim 3, further comprising a first bit line RBL, a second pole of a first transistor in each of the sub-output circuits and a second pole of the second transistor being connected to the first bit line RBL to form an output path.
5. The computing circuit of claim 4, wherein the first bit line RBL includes a first sub bit line RBL and a second sub bit line RBL, a second pole of the first transistor is connected to the first sub bit line RBL, a second pole of the second transistor is connected to the second sub bit line RBL, and the first transistor and the second transistor are configured to perform a charging operation or a discharging operation on the first sub bit line RBL and the second sub bit line RBL, respectively, under control of the computation output node voltage.
6. The computing circuit of claim 5, wherein the first sub-bit line RBL and the second sub-bit line RBL are connected by a computation result processing circuit including a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor; The calculation result processing circuit is configured to perform an average process on voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain calculation results of the plurality of calculation units.
7. A computing circuit as claimed in claim 3, wherein the sub-output circuit comprises a third capacitor, a first end of the third capacitor being connected to the computing output node.
8. The computing circuit of claim 7, further comprising a second bit line RBL, a second end of a third capacitor in each of the sub-output circuits being connected to the second bit line RBL; the third capacitor is configured to couple the voltage of the computing output node to the second bit line RBL.
9. The computing circuit of any of claims 1-6, wherein the first ferroelectric transistor and the second ferroelectric transistor are further configured to receive M times the signal input voltage based on M pulses after the precharge circuit adjusts the computing output node to the target voltage; The calculation result output circuit is used for respectively outputting the voltage of the calculation output node through N output channels after receiving the signal input voltage each time so as to obtain a second calculation result calculated by the multiplication calculation circuit through N times of coupling of the voltage of the calculation output node, wherein the second calculation result is calculated according to the signal input voltage and a second neural network weight value, the second neural network weight value is obtained according to the first neural network weight value and the pulse frequency M, and M is a positive integer.
10. The computing circuit of claim 1, wherein a first pole of the first ferroelectric transistor is connected to a first pole of the second ferroelectric transistor, a second pole of the first ferroelectric transistor is a first signal input node, a second pole of the second ferroelectric transistor is a second signal input node, a gate of the first ferroelectric transistor is a first write voltage drive node, and a gate of the second ferroelectric transistor is a second write voltage drive node; the first signal input node and the second signal input node are used for inputting the signal input voltage; The first write voltage driving node and the second write voltage driving node are used for inputting the write voltage.
11. The computing circuit of claim 10, wherein the compute output node is located between a first pole of the first ferroelectric transistor and a first pole of the second ferroelectric transistor.
12. The computing circuit of claim 1, wherein the precharge circuit comprises a third transistor having a source connected to a second voltage source for outputting the target voltage, a drain connected to the computing output node, and a gate for receiving a pulse signal to adjust the computing output node to the target voltage based on the pulse signal.
13. The computing circuit of claim 12, further comprising a word line WL; a gate of a third transistor in the precharge circuit in each of the calculation units is connected to the WL; the WL is configured to output the pulse signal to a gate of a third transistor in the precharge circuit in each of the computing units.

Description

Computing circuit Technical Field The application relates to the technical field of circuits, in particular to a computing circuit. Background Compared with a binary weight neural network or a three-value weight neural network, the multi-value weight neural network can use more bit numbers to represent weights and activation values, so that the multi-value weight neural network has better precision. In the prior art, a multi-value weight neural network is mostly implemented based on Static Random-Access Memory (SRAM). However, such a multi-value weighted neural network implemented based on SRAM is high in power consumption and low in integration. Disclosure of Invention In view of the above, it is necessary to provide a calculation circuit with low power consumption and high integration. The application provides a calculation circuit, which comprises a plurality of calculation units of different types, wherein the calculation units are arranged in an array, each calculation unit comprises a multiplication calculation circuit, a precharge circuit and a calculation result output circuit, the calculation result output circuits of the different types of calculation units are different, the multiplication calculation circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, the precharge circuit and the calculation result output circuit are electrically connected with calculation output nodes positioned between the first ferroelectric transistor and the second ferroelectric transistor, the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value, the precharge circuit is used for adjusting the calculation output nodes to the target voltage, the first ferroelectric transistor and the second ferroelectric transistor are used for receiving signal input voltages after the calculation output nodes are adjusted to the target voltage, the calculation result output circuits are used for respectively outputting the voltages of the calculation output nodes through N output channels after the signal input voltages are received, the first and second output nodes are coupled to obtain the calculation result values of the neural network according to N different from the N-type neural network, the number of the first neural network is different from the first neural network, the calculation result is obtained by coupling the first neural network, the N-type of the calculation result is different from the calculation result value, and the first neural network is obtained. In one embodiment, the calculation result output circuit includes N sub-output circuits, where each of the sub-output circuits is configured to output the voltage of the calculation output node through a different output path. In one embodiment, the sub-output circuit comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are both connected to the calculation output node, the first pole of the first transistor is connected to a first voltage source, and the first pole of the second transistor is grounded. In one embodiment, the computing circuit further includes a first bit line RBL, and the second pole of the first transistor and the second pole of the second transistor in each of the sub-output circuits are connected to the first bit line RBL to form an output path. In one embodiment, the first bit line RBL includes a first sub bit line RBL and a second sub bit line RBL, a second pole of the first transistor is connected to the first sub bit line RBL, a second pole of the second transistor is connected to the second sub bit line RBL, and the first transistor and the second transistor are used for performing a charging operation or a discharging operation on the first sub bit line RBL and the second sub bit line RBL, respectively, under the control of the calculated output node voltage. In one embodiment, the first sub-bit line RBL and the second sub-bit line RBL are connected by a computation result processing circuit, wherein the computation result processing circuit comprises a first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor, and the computation result processing circuit is used for carrying out averaging processing on the voltages of the first sub-bit line RBL and the second sub-bit line RBL so as to obtain computation results of the plurality of computation units. In one embodiment, the output circuit includes a third capacitor, a first end of which is connected to the computing output node. In one embodiment, the computing circuit further comprises a second bit line RBL, and a second end of a third capacitor in each sub-output circuit is connected with the second bit line RBL, wherein the third capacitor is used