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CN-117475813-B - Gate drive circuit and display panel

CN117475813BCN 117475813 BCN117475813 BCN 117475813BCN-117475813-B

Abstract

The invention discloses a gate driving circuit and a display panel. The grid driving circuit comprises a first control module, an output pull-up module, an output pull-down module and a second control module, wherein in a reset stage, a clock signal is low, a start signal is kept high, a sensing output signal is kept low, in an output stage after the reset stage, the clock signal is changed to be high, the start signal is kept high, the sensing output signal is changed from low to high, in a maintenance stage after the output stage, the clock signal is changed to be low, the start signal is changed to low, and the sensing output signal is kept high. According to the invention, only one group of clock signals is needed to reduce signal wiring and reduce the frame of the display panel, and the regulating step length for gradually transmitting the initial signal and the sensing output signal based on the clock signals is only two pulse widths of the clock signals, so that the regulating step length of the sensing output signal is reduced, and the accurate regulation and control of the compensation circuit are facilitated.

Inventors

  • LI HUA

Assignees

  • 深圳市华星光电半导体显示技术有限公司

Dates

Publication Date
20260512
Application Date
20230309

Claims (10)

  1. 1. A gate driving circuit, comprising: the first control module is connected with the first node, and is connected with the clock signal, the starting signal and the first low potential signal, and is used for controlling the potential of the first node; The output pull-up module is connected with the first node and is connected with a high potential signal, and is used for outputting and pulling up the potential of a sensing output signal, the initial signal is a signal of a previous stage of the sensing output signal, and the initial signal and the sensing output signal are pulse signals; The output pull-down module is connected with the first control module and the second node, and is connected with a second low potential signal for pulling down the potential of the sensing output signal; the second control module is connected with the first node and the second node, and is connected with the high potential signal, the hierarchical transmission signal and the starting signal, and is used for maintaining the low potential of the second node; In a reset stage, the clock signal is at a low potential, the start signal is kept at a high potential, the first node is at a low potential, the second node is at a high potential, and the sensing output signal is kept at a low potential; In an output stage following the reset stage, the clock signal becomes high, the start signal remains high, the second node becomes low, the first node becomes high, and the sense output signal changes from low to high; in a maintenance stage after the output stage, the clock signal is turned into low potential, the initial signal is turned into low potential, the first node maintains high potential, the second node maintains low potential, and the sensing output signal maintains high potential so as to realize step-by-step transmission of the initial signal and the sensing output signal, wherein the regulating step length of the step-by-step transmission is two pulse widths of the clock signal.
  2. 2. The gate drive circuit of claim 1, wherein the second control module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first storage capacitor, wherein a gate electrode and a first electrode of the first transistor and a gate electrode of the second transistor are connected to the level transmission signal, a first electrode of the second transistor and a second electrode of the first transistor are connected to a third node, a second electrode of the second transistor and a gate electrode of the third transistor are connected to a fourth node, a first electrode of the third transistor is connected to the high potential signal, a second electrode of the third transistor and a third node are connected, one end of the first storage capacitor is connected to the fourth node, the other end of the first storage capacitor is connected to the high potential signal, a gate electrode of the fourth transistor and the fourth node are connected to the level transmission signal, a first electrode of the second transistor and a second electrode of the third transistor are connected to the third node, a second electrode of the second transistor and a second electrode of the third transistor and a third electrode of the third transistor are connected to the high potential signal, a second electrode of the seventh transistor and a third electrode of the seventh transistor are connected to the first node, and a third electrode of the seventh transistor are connected to the first node.
  3. 3. The gate driving circuit according to claim 2, wherein the second control module further comprises an eighth transistor, a gate of the eighth transistor is connected to a gate of the sixth transistor and a gate of the seventh transistor, and the start signal is simultaneously connected, a first electrode of the eighth transistor is connected to the first low potential signal, and a second electrode of the eighth transistor is connected to the second node.
  4. 4. The gate driving circuit of claim 2, wherein the second control module further comprises a ninth transistor and a tenth transistor, wherein a gate of the ninth transistor is connected to the clock signal, a first electrode is connected to a gate of the sixth transistor and a gate of the seventh transistor, and is simultaneously connected to the start signal, a second electrode is connected to a gate of the tenth transistor, a first electrode of the tenth transistor is connected to the first low potential signal, and a second electrode is connected to the second node.
  5. 5. The gate driving circuit of claim 1, wherein the first control module comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second storage capacitor, wherein the gate of the eleventh transistor is connected to the clock signal, the first electrode is connected to the start signal, the second electrode is connected to the first node, the gate of the twelfth transistor and the gate of the thirteenth transistor are simultaneously connected to the second node, the first electrode of the twelfth transistor is connected to the first node, the second electrode is connected to the first electrode of the thirteenth transistor and the third node, the second electrode of the thirteenth transistor is connected to the first low potential signal, the gate of the fourteenth transistor is connected to the first node, the first electrode is connected to the high potential signal, the second electrode is connected to the third node, one end of the second storage capacitor is connected to the first node, and the other end of the second storage capacitor is connected to the sense output signal.
  6. 6. The gate driving circuit of claim 1, wherein the output pull-up module comprises a fifteenth transistor, a gate of the fifteenth transistor is connected to the first node, a first electrode is connected to the high potential signal, and a second electrode is connected to the sense output signal.
  7. 7. The gate driving circuit of claim 1, wherein the output pull-down module comprises a sixteenth transistor having a gate connected to the second node, a first electrode connected to the second low potential signal, and a second electrode connected to the sense output signal.
  8. 8. The gate driving circuit of claim 1, wherein the start signal is low, the first node is pulled low, the level signal is high, the second node is pulled high, the output pull-down module is turned on, and the sense output signal goes low at an end stage following the sustain stage.
  9. 9. The gate drive circuit according to claim 1, wherein the clock signal is a positive-phase clock signal or a negative-phase clock signal, the positive-phase clock signal being opposite in potential to the negative-phase clock signal, and a duty ratio of the clock signal is 40% to 60%.
  10. 10. A display panel comprising an array substrate and the gate driving circuit of any one of claims 1 to 9, the gate driving circuit being connected to the array substrate.

Description

Gate drive circuit and display panel Technical Field The present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a display panel. Background In the internal compensation circuit of partial pixels of the display panel, the gate driving circuit is required to output a pulse signal with adjustable width for the purpose of compensating and adjusting the display panel, because of the requirement of compensation precision. The current method for realizing pulse width regulation mainly utilizes two control signals, and because the control signals must have step-by-step transmissibility, two groups of clock signals are required to generate two groups of step-by-step transmission control signals, so that more signal wires are needed, and the frame of the display panel is enlarged. On the other hand, the step length of the output pulse signal, which can be regulated and controlled, is larger, which is not beneficial to the accurate regulation and control of the compensation effect. Disclosure of Invention Based on the shortcomings in the prior art, the invention aims to provide a grid driving circuit and a display panel, only one group of clock signals are needed, signal wiring can be reduced, the frame of the display panel is reduced, the regulation step length of sensing output signals is reduced, and the accurate regulation and control of a compensation circuit are facilitated. To achieve the above object, the present invention provides a gate driving circuit, comprising: The first control module is connected with the first node, and is connected with the clock signal, the start signal and the first low potential signal, and is used for controlling the potential of the first node; The output pull-up module is connected with the first node and is connected with a high potential signal, and is used for outputting and pulling up the potential of the sensing output signal, wherein the initial signal is a previous-stage signal of the sensing output signal, and the initial signal and the sensing output signal are pulse signals; The output pull-down module is connected with the first control module and the second node, and is connected with a second low-potential signal for pulling down the potential of the sensing output signal; the second control module is connected with the first node and the second node, and is connected with the high potential signal, the level transmission signal and the starting signal, and is used for maintaining the low potential of the second node; in the reset stage, the clock signal is at low potential, the initial signal is kept at high potential, the first node is at low potential, the second node is at high potential, and the sensing output signal is kept at low potential; in an output stage after the reset stage, the clock signal becomes high, the start signal remains high, the second node becomes low, the first node becomes high, and the sense output signal changes from low to high; In the maintaining stage after the output stage, the clock signal is turned into low potential, the initial signal is turned into low potential, the first node maintains high potential, the second node maintains low potential, and the sensing output signal maintains high potential, so that the step-by-step transmission of the initial signal and the sensing output signal is realized, and the regulating step length of the step-by-step transmission is two pulse widths of the clock signal. Optionally, the second control module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first storage capacitor, wherein the grid electrode and the first electrode of the first transistor and the grid electrode of the second transistor are connected with the level transmission signals, the first electrode of the second transistor and the second electrode of the first transistor are connected to a third node, the grid electrode of the third transistor is connected to a fourth node, the first electrode of the third transistor is connected with a high potential signal, the second electrode of the third transistor is connected with the third node, one end of the first storage capacitor is connected with the fourth node, the other end of the first storage capacitor is connected with the high potential signal, the grid electrode of the fourth transistor is connected with the fourth node, the first electrode of the first storage capacitor is connected with the high potential signal, the second electrode of the third storage capacitor is connected with the second node, the grid electrode of the fifth transistor is connected with the first node, the first electrode of the first transistor is connected with the first low potential signal, the second electrode of the second transistor is connected with the second node, the grid electrode of the sixth transistor and the grid e