CN-117494772-B - Computing circuit

Abstract

The application relates to a computing circuit, which comprises a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, the computing result output circuit comprises N output channels and is used for turning off M output channels in the N output channels according to a first target voltage signal, after receiving a signal input voltage, the computing circuit is used for respectively executing charging operation or discharging operation according to the N-M output channels under the control of a computing output node voltage, the computing result obtained by the multiplication computing circuit of the computing unit is obtained through the N-M charging operation or discharging operation, and the computing result is obtained by the computing unit according to the signal input voltage and a first neural network weight value, and the first neural network weight value is obtained according to an initial neural network weight value and the times of the charging operation or the discharging operation. The computing circuit provided by the application can reduce the power consumption and improve the integration level.

Inventors

• REN TIANLING
• WANG ZHENZE
• YAN ANZHI
• YAN ZHAOYI
• LIU HOUFANG
• YANG DIE

Assignees

• 清华大学

Dates

Publication Date

20260512

Application Date

20230927

Claims (16)

1. 1. The computing circuit is characterized by comprising a plurality of computing units of different types, wherein the computing units are arranged in an array, each computing unit comprises a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the computing units of different types are different; the multiplication calculating circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are connected with each other, and the precharge circuit and the calculation result output circuit are electrically connected with a calculation output node between the first ferroelectric transistor and the second ferroelectric transistor; The first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the drive of write voltage so as to represent an initial neural network weight value; the precharge circuit is used for adjusting the calculation output node to a target voltage; The first ferroelectric transistor and the second ferroelectric transistor are used for receiving a signal input voltage after the calculation output node is adjusted to the target voltage; The calculation result output circuit comprises N output channels and is used for turning off M output channels in the N output channels according to a first target voltage signal so as to respectively execute charging operation or discharging operation according to N-M output channels under the control of the calculation output node voltage after receiving the signal input voltage, so as to obtain a calculation result calculated by the multiplication calculation circuit of the calculation unit through N-M times of charging operation or discharging operation, wherein the calculation result is a calculation result calculated by the calculation unit according to the signal input voltage and a first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the times N-M of the charging operation or the discharging operation, and N and M are positive integers.
2. 2. The computing circuit of claim 1, wherein the computation result output circuit comprises N sub-output circuits, wherein each of the sub-output circuits is configured to perform the charging operation or the discharging operation through a different output path.
3. 3. The computing circuit of claim 2, wherein the sub-output circuit comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor each being connected to the computing output node.
4. 4. A calculation circuit according to claim 3, wherein said calculation result output circuit is configured to perform adjustment processing on voltages of first poles of first transistors and second transistors in the M output paths according to the first target voltage signal to turn off the M output paths.
5. 5. The calculation circuit according to claim 3, wherein the calculation result output circuit is further configured to perform adjustment processing on voltages of first poles of the first transistors and the second transistors in the N output paths according to a second target voltage signal for respectively performing the charging operation or the discharging operation according to the N output paths under control of voltages of the calculation output nodes after receiving the signal input voltages, the second target voltage signal being used to adjust a charging current or a discharging current when the N output paths perform the charging operation or the discharging operation respectively to a target charging current or a target discharging current, the target charging current being half of the charging current, the target discharging current being half of the discharging current, so as to obtain the calculation result calculated by the multiplication calculation circuit of the calculation unit by performing N charging operations or the discharging operations through the N output paths; The calculation result is calculated by the calculation unit according to the signal input voltage and a second neural network weight value, and the second neural network weight value is half of the initial neural network weight value.
6. 6. The computing circuit of claim 1, wherein the computing circuit comprises a plurality of first computing groups, each of the first computing groups comprises four computing units, namely a first computing unit, a second computing unit, a third computing unit and a fourth computing unit, the computing result output circuits of the first computing unit and the third computing unit each comprise one output path, and the computing result output circuits of the second computing unit and the fourth computing unit each comprise two output paths; The first ferroelectric transistors and the second ferroelectric transistors of the four computing units are used for receiving different signal input voltages after the computing output nodes are adjusted to the target voltages; A calculation result output circuit of the second calculation unit and the fourth calculation unit for turning off one of the two output paths according to the first target voltage signal to perform the charging operation or the discharging operation according to one of the output paths under control of the voltage of the calculation output node after receiving the signal input voltage; And the calculation result output circuits of the first calculation unit and the third calculation unit are used for executing the charging operation or the discharging operation according to the output path under the control of the voltage of the calculation output node after receiving the signal input voltage.
7. 7. The computing circuit of claim 1, wherein the computing circuit comprises a plurality of second computing groups, each of the second computing groups comprises four computing units, namely a first computing unit, a second computing unit, a third computing unit and a fourth computing unit, wherein the computing result output circuits of the first computing unit and the third computing unit each comprise one output path, and the computing result output circuits of the second computing unit and the fourth computing unit each comprise two output paths; The first ferroelectric transistor and the second ferroelectric transistor of the first computing unit and the second computing unit are used for receiving a first signal input voltage after the computing output node is adjusted to the target voltage, and the first ferroelectric transistor and the second ferroelectric transistor of the third computing unit and the fourth computing unit are used for receiving a second signal input voltage after the computing output node is adjusted to the target voltage; The calculation result output circuit of the second calculation unit and the fourth calculation unit is used for executing the charging operation or the discharging operation according to the two output paths under the control of the voltage of the calculation output node after receiving the first signal input voltage and the second signal input voltage; And the calculation result output circuits of the first calculation unit and the third calculation unit are used for executing the charging operation or the discharging operation according to the output path under the control of the voltage of the calculation output node after receiving the first signal input voltage and the second signal input voltage.
8. 8. The computing circuit of claim 1, wherein the computing circuit comprises a plurality of third computing groups, each third computing group comprises four computing units, namely a first computing unit, a second computing unit, a third computing unit and a fourth computing unit, the computing result output circuits of the first computing unit and the third computing unit each comprise one output path, and the computing result output circuits of the second computing unit and the fourth computing unit each comprise two output paths; The first ferroelectric transistors and the second ferroelectric transistors of the four computing units are used for receiving the same signal input voltage after the computing output nodes are adjusted to the target voltage; a calculation result output circuit of the first calculation unit, configured to perform the charging operation or the discharging operation according to the one output path under control of the voltage of the calculation output node after receiving the signal input voltage; The calculation result output circuit of the second calculation unit is used for executing the charging operation or the discharging operation according to the two output paths under the control of the voltage of the calculation output node after receiving the signal input voltage; a calculation result output circuit of the third calculation unit, configured to perform adjustment processing on voltages of a first transistor and a first pole of a second transistor in one of the output paths according to the first target voltage signal, so as to perform the charging operation or the discharging operation according to one of the output paths under control of the voltage of the calculation output node after receiving the signal input voltage; And the calculation result output circuit of the fourth calculation unit is used for adjusting the voltages of the first poles of the first transistor and the second transistor in the two output paths according to a second target voltage signal so as to execute the charging operation or the discharging operation according to the two output paths under the control of the voltage of the calculation output node after receiving the signal input voltage.
9. 9. The computing circuit of claim 8, wherein the computing circuit is configured to, The calculation result output circuit of the fourth calculation unit is further configured to turn off one of the two output paths according to the first target voltage signal, so as to perform the charging operation or the discharging operation according to one of the output paths under control of the voltage of the calculation output node after receiving the signal input voltage.
10. 10. The computing circuit of claim 6, further comprising a first bitline RBL and a second bitline RBL, the first bitline RBL comprising a first sub bitline RBL1 and a first sub bitline RBL2, the second bitline RBL comprising a second sub bitline RBL1 and a second sub bitline RBL2; a second pole of a first transistor in a calculation result output circuit in the first calculation unit and the second calculation unit is connected with the first sub-bit line RBL1, and a second pole of a second transistor in a calculation result output circuit in the first calculation unit and the second calculation unit is connected with the second sub-bit line RBL 1; The second poles of the first transistors in the calculation result output circuits of the third calculation unit and the fourth calculation unit are connected with the first sub bit line RBL2, and the second poles of the second transistors in the calculation result output circuits of the third calculation unit and the fourth calculation unit are connected with the second sub bit line RBL 2.
11. 11. The computing circuit of claim 10, wherein the first sub-bit line RBL1 and the second sub-bit line RBL1 are connected by a first computation result processing circuit, the first sub-bit line RBL2 and the second sub-bit line RBL2 are connected by a second computation result processing circuit, each of the first computation result processing circuit and the second computation result processing circuit including a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor; The calculation result processing circuit is configured to perform an average process on voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain calculation results of the plurality of calculation units.
12. 12. The computing circuit of claim 6, wherein a first pole of the first ferroelectric transistor is connected to a first pole of the second ferroelectric transistor, a second pole of the first ferroelectric transistor is a first signal input node, a second pole of the second ferroelectric transistor is a second signal input node, a gate of the first ferroelectric transistor is a first write voltage drive node, and a gate of the second ferroelectric transistor is a second write voltage drive node; the first signal input node and the second signal input node are used for inputting the signal input voltage; The first write voltage driving node and the second write voltage driving node are used for inputting the write voltage.
13. 13. The computing circuit of claim 12, wherein the compute output node is located between a first pole of the first ferroelectric transistor and a first pole of the second ferroelectric transistor.
14. 14. The computing circuit of claim 13, wherein the precharge circuit comprises a third transistor having a source connected to a second voltage source for outputting the target voltage, a drain connected to the computing output node, and a gate for receiving a pulse signal to adjust the computing output node to the target voltage based on the pulse signal.
15. 15. The computing circuit of claim 14, further comprising a word line WL; a gate of a third transistor in the precharge circuit in each of the calculation units is connected to the WL; the WL is configured to output the pulse signal to a gate of a third transistor in the precharge circuit in each of the computing units.
16. 16. The computing circuit of claim 15, wherein the word line WL comprises a first word line WL and a second word line WL; The gates of the third transistors in the precharge circuits in the first calculation unit and the second calculation unit are connected with the first word line WL; Gates of third transistors in the precharge circuits in the third and fourth calculation units are connected to the second word line WL.

Description

Computing circuit Technical Field The application relates to the technical field of circuits, in particular to a computing circuit. Background The weight reconfigurable neural network (Reconfigurable Neural Network Array Circuits, RNNA) is a neural network architecture with reconfigurability, the weights of which can be modified at runtime to adapt to different tasks and application scenarios. In the prior art, a weight reconfigurable neural network is mostly implemented based on Static Random-Access Memory (SRAM). However, the weight reconfigurable neural network realized based on the SRAM has higher power consumption and lower integration level. Disclosure of Invention In view of the foregoing, it is necessary to provide a computing circuit with low power consumption and high integration level, which can implement a weight reconfigurable neural network. The application provides a calculation circuit, which comprises a plurality of calculation units of different types, wherein the calculation units are arranged in an array, each calculation unit comprises a multiplication calculation circuit, a precharge circuit and a calculation result output circuit, the calculation result output circuits of the calculation units of different types are different, the multiplication calculation circuit comprises a first ferroelectric transistor and a second ferroelectric transistor which are mutually connected, the precharge circuit and the calculation result output circuit are electrically connected with calculation output nodes positioned between the first ferroelectric transistor and the second ferroelectric transistor, the first ferroelectric transistor and the second ferroelectric transistor are used for entering a target resistance state under the driving of a write voltage so as to represent an initial neural network weight value, the precharge circuit is used for adjusting the calculation output nodes to a target voltage, the first ferroelectric transistor and the second ferroelectric transistor are used for receiving signal input voltages after the calculation output nodes are adjusted to the target voltage, the calculation result output circuit comprises N output paths and is used for turning off M output paths in the N output paths according to the first target voltage signals, the calculation result output signals are obtained through the calculation result output nodes, the calculation unit is controlled to obtain a calculation result by the charge-discharge operation of the calculation unit under the control of the calculation result input voltage according to the calculation result, the calculation result is calculated by the calculation unit, the calculation result is obtained through the operation of M-M output nodes, the calculation result is calculated by the calculation unit, and the calculation result is calculated by the operation of the calculation unit, the first neural network weight value is obtained according to the initial neural network weight value and the number N-M of the charging operation or the discharging operation, wherein N and M are positive integers. In one embodiment, the calculation result output circuit includes N sub-output circuits, wherein each of the sub-output circuits is configured to perform the charging operation or the discharging operation through a different output path. In one embodiment, the sub-output circuit includes a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor being connected to the compute output node. In one embodiment, the calculation result output circuit is configured to perform adjustment processing on voltages of a first pole of the first transistor and a first pole of the second transistor in the M output paths according to the first target voltage signal, so as to turn off the M output paths. In one embodiment, the calculation result output circuit is further configured to adjust voltages of first poles of the first transistors and the second transistors in the N output paths according to the second target voltage signal, so as to respectively perform the charging operation or the discharging operation according to the N output paths under the control of the voltage of the calculation output node after receiving the signal input voltage, where the second target voltage signal is used to adjust a charging current or a discharging current when the N output paths respectively perform the charging operation or the discharging operation to be a target charging current or a target discharging current, the target charging current is half of the charging current, the target discharging current is half of the discharging current, and a calculation result calculated by the multiplication calculation circuit of the calculation unit is obtained by performing the N charging operations or the discharging operation through the N output paths, and the calculation result is a calculation result calculat