CN-117501352-B - Pixel circuit, driving method thereof, display substrate and display device

Abstract

A pixel circuit, a driving method thereof, a display substrate and a display device are provided, wherein the pixel circuit is arranged in the display substrate, the display substrate comprises a display stage and a non-display stage, the pixel circuit is arranged to drive a light emitting element to emit light in the display stage, the pixel circuit comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light emitting control sub-circuit and a driving sub-circuit, the third control sub-circuit is respectively and electrically connected with a third reset signal end, a control signal end and a third node, the third control sub-circuit is arranged to provide a first signal to the third node in the display stage under the control of the third reset signal end, provide a second signal to the third node in the non-display stage or acquire a signal of the third node, the voltage value of the first signal is smaller than the voltage value of the signal of the third initial signal end, and the voltage value of the second signal is larger than the voltage value of the signal of the third initial signal end.

Inventors

• WANG RUI
• HU MING
• QIU HAIJUN
• CHEN JUNTAO

Assignees

• 京东方科技集团股份有限公司
• 重庆京东方显示技术有限公司

Dates

Publication Date

20260508

Application Date

20220530

Claims (20)

1. 1. A pixel circuit provided in a display substrate including a display stage and a non-display stage, the pixel circuit being provided to drive a light emitting element to emit light in the display stage, and including a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light emission control sub-circuit, and a driving sub-circuit; The first control sub-circuit is electrically connected with the first power supply end, the second scanning signal end, the first reset signal end, the second reset signal end, the first initial signal end, the second initial signal end, the first node, the third node and the fourth node respectively, and is configured to provide signals of the first initial signal end or the third node for the first node under the control of the first reset signal end and the second scanning signal end, and provide signals of the second initial signal end for the fourth node under the control of the second reset signal end; The second control sub-circuit is electrically connected with the first scanning signal end, the third reset signal end, the third initial signal end, the data signal end and the second node respectively, and is configured to provide signals of the third initial signal end or the data signal end for the second node under the control of the third reset signal end and the first scanning signal end; the third control sub-circuit is respectively and electrically connected with the third reset signal end, the control signal end and the third node, and is arranged to provide a first signal for the third node in a display stage and provide a second signal for the third node or acquire a signal of the third node in a non-display stage under the control of the third reset signal end; The driving sub-circuit is respectively and electrically connected with the first node, the second node and the third node and is used for providing driving current for the third node under the control of the first node and the second node; The light-emitting control sub-circuit is respectively and electrically connected with the light-emitting signal end, the first power end, the second node, the third node and the fourth node, and is arranged to provide a signal of the first power end for the second node and a signal of the third node for the fourth node under the control of the light-emitting signal end; the light-emitting element is respectively and electrically connected with the fourth node and the second power supply end; The voltage value of the first signal is smaller than the voltage value of the signal of the third initial signal end, and the voltage value of the second signal is larger than the voltage value of the signal of the third initial signal end.
2. 2. The pixel circuit according to claim 1, wherein, in the display stage, when the signal of the first reset signal terminal is an active level signal, the signal of the third reset signal terminal is an active level signal, and the signals of the first scan signal terminal, the second scan signal terminal, and the light emitting signal terminal are inactive level signals; When the first scanning signal end is an effective level signal, the signal of the second scanning signal end is an effective level signal, and the signals of the first reset signal end, the third reset signal end and the light-emitting signal end are invalid level signals; the voltage values of the signals of the first initial signal end, the second initial signal end and the third initial signal end are constant.
3. 3. The pixel circuit according to claim 2, wherein, in the display stage, the occurrence time of the signal of the second reset signal terminal being the active level signal is before the occurrence time of the signal of the first reset signal terminal being the active level signal, or the occurrence time of the signal of the second reset signal terminal being the active level signal is within the occurrence time of the signal of the third reset signal terminal being the active level signal, or the occurrence time of the signal of the second reset signal terminal being the active level signal is within the occurrence time of the signal of the first scan signal terminal being the active level signal, or the occurrence time of the signal of the second reset signal terminal being the active level signal is after the occurrence time of the signal of the first scan signal terminal being the active level signal.
4. 4. A pixel circuit according to claim 3, wherein when the occurrence time of the signal of the second reset signal terminal being an active level signal is within the occurrence time of the signal of the third reset signal terminal being an active level signal, the signal of the second reset signal terminal is identical to the signal of the third reset signal terminal; When the occurrence time of the signal of the second reset signal end which is the effective level signal is within the occurrence time of the signal of the first scanning signal end which is the effective level signal, the signal of the second reset signal end is the same as the signal of the first scanning signal end.
5. 5. The pixel circuit of claim 1 wherein the first control sub-circuit comprises a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit; The first reset sub-circuit is electrically connected with the first reset signal end, the first initial signal end and the first node respectively and is used for providing signals of the first initial signal end for the first node under the control of the first reset signal end; The second reset sub-circuit is electrically connected with the second reset signal end, the second initial signal end and the fourth node respectively and is used for providing signals of the second initial signal end for the fourth node under the control of the second reset signal end; the compensation sub-circuit is respectively and electrically connected with the first node, the third node and the second scanning signal end and is arranged to provide the signal of the third node for the first node under the control of the second scanning signal end; The storage sub-circuit is electrically connected with the first power end and the first node respectively and is used for storing the voltage difference between the signal of the first power end and the signal of the first node.
6. 6. The pixel circuit of claim 1 wherein said second control sub-circuit comprises a third reset sub-circuit and a write sub-circuit; The third reset sub-circuit is electrically connected with the third reset signal end, the third initial signal end and the second node respectively and is used for providing signals of the third initial signal end for the second node under the control of the third reset signal end; The write sub-circuit is electrically connected with the first scanning signal end, the data signal end and the second node respectively, and is configured to provide signals of the data signal end for the second node under the control of the first scanning signal end.
7. 7. The pixel circuit of claim 5 wherein the first reset sub-circuit comprises a first transistor and the second reset sub-circuit comprises a seventh transistor, the compensation sub-circuit comprises a second transistor, and the storage sub-circuit comprises a capacitor comprising a first plate and a second plate; the control electrode of the first transistor is electrically connected with the first reset signal end, the first electrode of the first transistor is electrically connected with the first initial signal end, and the second electrode of the first transistor is electrically connected with the first node; the control electrode of the second transistor is electrically connected with the second scanning signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the seventh transistor is electrically connected with the second reset signal end, the first electrode of the seventh transistor is electrically connected with the second initial signal end, and the second electrode of the seventh transistor is electrically connected with the fourth node; The first polar plate of the capacitor is electrically connected with the first node, and the second polar plate of the capacitor is electrically connected with the first power end.
8. 8. The pixel circuit of claim 6 wherein the write sub-circuit comprises a fourth transistor and the third reset sub-circuit comprises an eighth transistor; The control electrode of the fourth transistor is electrically connected with the first scanning signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the eighth transistor is electrically connected with the third reset signal end, the first electrode of the eighth transistor is electrically connected with the third initial signal end, and the second electrode of the eighth transistor is electrically connected with the second node.
9. 9. The pixel circuit of claim 1, wherein the third control sub-circuit comprises a ninth transistor; the control electrode of the ninth transistor is electrically connected with the third reset signal end, the first electrode of the ninth transistor is electrically connected with the control signal end, and the second electrode of the ninth transistor is electrically connected with the third node.
10. 10. The pixel circuit of claim 1 wherein the first control sub-circuit comprises a first transistor, a second transistor, a seventh transistor, and a capacitor, the capacitor comprising a first plate and a second plate, the second control sub-circuit comprising a fourth transistor and an eighth transistor, the third control sub-circuit comprising a ninth transistor, the drive sub-circuit comprising a third transistor, the light emission control sub-circuit comprising a fifth transistor and a sixth transistor; the control electrode of the first transistor is electrically connected with the first reset signal end, the first electrode of the first transistor is electrically connected with the first initial signal end, and the second electrode of the first transistor is electrically connected with the first node; the control electrode of the second transistor is electrically connected with the second scanning signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the first scanning signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power end, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node; The control electrode of the seventh transistor is electrically connected with the second reset signal end, the first electrode of the seventh transistor is electrically connected with the second initial signal end, and the second electrode of the seventh transistor is electrically connected with the fourth node; the control electrode of the eighth transistor is electrically connected with the third reset signal end, the first electrode of the eighth transistor is electrically connected with the third initial signal end, and the second electrode of the eighth transistor is electrically connected with the second node; a control electrode of the ninth transistor is electrically connected with the third reset signal end, a first electrode of the ninth transistor is electrically connected with the control signal end, and a second electrode of the ninth transistor is electrically connected with the third node; The first polar plate of the capacitor is electrically connected with the first node, and the second polar plate of the capacitor is electrically connected with the first power end.
11. 11. The pixel circuit according to claim 10, wherein the first transistor and the second transistor are opposite in transistor type from the third transistor to the ninth transistor; The first transistor and the second transistor are oxide transistors and are N-type transistors.
12. 12. A display substrate comprising a base, and a circuit structure layer and a light emitting structure layer sequentially provided on the base, wherein the light emitting structure layer comprises light emitting elements, and the circuit structure layer comprises pixel circuits according to any one of claims 1 to 11 arranged in an array.
13. 13. The display substrate according to claim 12, wherein when the occurrence time of the signal of the second reset signal terminal being the active level signal is before the occurrence time of the signal of the first reset signal terminal being the active level signal, the signal of the second reset signal terminal of the i-th row pixel circuit is identical to the signal of the first scan signal terminal of the i-1 th row pixel circuit; When the signal of the second reset signal end is the effective level signal and the occurrence time of the signal of the first scanning signal end is after the occurrence time of the effective level signal, the signal of the second reset signal end of the pixel circuit of the ith row is the same as the signal of the first scanning signal end of the pixel circuit of the (i+1) th row.
14. 14. The display substrate of claim 12, wherein the circuit structure layer further comprises a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of light emitting signal lines and a plurality of control signal lines, and a plurality of first power supply lines and a plurality of data signal lines extending in a first direction and arranged in a second direction, the first direction intersecting the second direction; The first reset signal end of the pixel circuit is electrically connected with the first reset signal wire, the second reset signal end is electrically connected with the second reset signal wire, the third reset signal end is electrically connected with the third reset signal wire, the first scanning signal end is electrically connected with the first scanning signal wire, the second scanning signal end is electrically connected with the second scanning signal wire, the light emitting signal end is electrically connected with the light emitting signal wire, the first initial signal end is electrically connected with the first initial signal wire, the second initial signal end is electrically connected with the second initial signal wire, the control signal end is electrically connected with the control signal wire, the first power end is electrically connected with the first power wire, and the data signal end is electrically connected with the data signal wire.
15. 15. The display substrate according to claim 14, further comprising a first chip connected to the control signal line and a second chip connected to the data signal line; The first chip is arranged to provide a first signal to the control signal line in a display stage, provide a second signal to the control signal line in a non-display stage, or acquire a signal of the control signal line, and further arranged to obtain a threshold voltage of the third transistor according to the signal of the control signal line, generate a control signal according to the threshold voltage of the third transistor, and send the control signal to the second chip; The second chip provides signals to the data signal lines according to the control signals.
16. 16. The display substrate according to claim 14, wherein the pixel structures of adjacent pixel circuits located in the same row are symmetrical with respect to a dummy straight line extending in the second direction; the adjacent pixel circuits located in the same row as the pixel circuits include a first adjacent pixel circuit and a second adjacent pixel circuit.
17. 17. The display substrate according to claim 14 or 16, wherein the pixel circuit comprises first to ninth transistors, a control electrode of the first transistor and a control electrode of the second transistor each comprising a first control electrode and a second control electrode; The first reset signal line comprises a first sub reset signal line and a second sub reset signal line which are arranged in different layers and are connected with each other, wherein the first sub reset signal line is arranged on the same layer as a first control electrode of the first transistor, and the second sub reset signal line is arranged on the same layer as a second control electrode of the first transistor; The second scanning signal line comprises a first sub-scanning signal line and a second sub-scanning signal line which are arranged in different layers and are connected with each other, the first sub-scanning signal line is arranged on the same layer as the first control electrode of the second transistor, and the second sub-scanning signal line is arranged on the same layer as the second control electrode of the second transistor.
18. 18. The display substrate of claim 17, wherein the pixel circuit further comprises a capacitor comprising a first electrode plate and a second electrode plate, wherein the circuit structure layer comprises a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a seventh insulating layer, a first planarization layer, and a fifth conductive layer sequentially stacked on the substrate; the first semiconductor layer includes active layers of third to ninth transistors in at least one pixel circuit; The first conductive layer comprises a first scanning signal line, a light emitting signal line, a first polar plate of a capacitor positioned in at least one pixel circuit, a control electrode of a third transistor and a control electrode of a ninth transistor; The second conductive layer comprises a first initial signal line, a first sub-reset signal line, a first sub-scanning signal line, a control signal line, a second polar plate of a capacitor positioned in at least one pixel circuit, a first control electrode of a first transistor and a first control electrode of a second transistor; The second semiconductor layer comprises an active layer of a first transistor, an active layer of a second transistor and an active connection part, which are positioned in at least one pixel circuit; The third conductive layer includes a second sub-reset signal line, a second sub-scan signal line, a third reset signal line, and a third initial signal line, and a second control electrode of the first transistor and a second control electrode of the second transistor in at least one pixel circuit; The fourth conductive layer includes a second initial signal line, and first and second poles of a first transistor, first and second poles of a second transistor, first and second poles of a fourth transistor, first and second poles of a fifth transistor, first and second poles of a sixth transistor, first and second poles of a seventh transistor, first and second poles of an eighth transistor, first and first connection electrodes of a ninth transistor in at least one pixel circuit; The fifth conductive layer includes a first power line, a data signal line, and a second connection electrode at the at least one pixel circuit, the second connection electrode being configured to connect the second electrode of the sixth transistor and the light emitting element.
19. 19. The display substrate according to claim 18, wherein the circuit structure layer further comprises a light shielding layer on a side of the first insulating layer close to the base, the light shielding layer comprising light shielding portions and light shielding connection portions arranged in an array and spaced apart from each other, the light shielding connection portions being arranged to connect adjacent light shielding portions; The orthographic projection of the light shielding part on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate.
20. 20. A display substrate according to claim 18 or 19, wherein the control electrode of the eighth transistor and the control electrode of the ninth transistor are of unitary construction; the first scanning signal line and the light-emitting signal line connected with the pixel circuit are respectively positioned at two sides of the first polar plate of the capacitor of the pixel circuit, and the integrated structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor is positioned between the first polar plate of the capacitor and the light-emitting signal line connected with the pixel circuit.

Description

Pixel circuit, driving method thereof, display substrate and display device Technical Field The disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, a display substrate and a display device. Background Organic LIGHT EMITTING Diodes (OLED) and Quantum-dot LIGHT EMITTING Diodes (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, light weight, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and a thin film transistor (Thin Film Transistor, abbreviated as TFT) for signal control has become a mainstream product in the current Display field. Disclosure of Invention The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims. In a first aspect, the present disclosure provides a pixel circuit disposed in a display substrate, the display substrate including a display stage and a non-display stage, the pixel circuit being configured to drive a light emitting element to emit light in the display stage, and including a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light emission control sub-circuit, and a driving sub-circuit; The first control sub-circuit is electrically connected with the first power supply end, the second scanning signal end, the first reset signal end, the second reset signal end, the first initial signal end, the second initial signal end, the first node, the third node and the fourth node respectively, and is configured to provide signals of the first initial signal end or the third node for the first node under the control of the first reset signal end and the second scanning signal end, and provide signals of the second initial signal end for the fourth node under the control of the second reset signal end; The second control sub-circuit is electrically connected with the first scanning signal end, the third reset signal end, the third initial signal end, the data signal end and the second node respectively, and is configured to provide signals of the third initial signal end or the data signal end for the second node under the control of the third reset signal end and the first scanning signal end; the third control sub-circuit is respectively and electrically connected with the third reset signal end, the control signal end and the third node, and is arranged to provide a first signal for the third node in a display stage and provide a second signal for the third node or acquire a signal of the third node in a non-display stage under the control of the third reset signal end; The driving sub-circuit is respectively and electrically connected with the first node, the second node and the third node and is used for providing driving current for the third node under the control of the first node and the second node; The light-emitting control sub-circuit is respectively and electrically connected with the light-emitting signal end, the first power end, the second node, the third node and the fourth node, and is arranged to provide a signal of the first power end for the second node and a signal of the third node for the fourth node under the control of the light-emitting signal end; the light-emitting element is respectively and electrically connected with the fourth node and the second power supply end; The voltage value of the first signal is smaller than the voltage value of the signal of the third initial signal end, and the voltage value of the second signal is larger than the voltage value of the signal of the third initial signal end. In some possible implementations, in the display stage, when the signal of the first reset signal terminal is an active level signal, the signal of the third reset signal terminal is an active level signal, and the signals of the first scan signal terminal, the second scan signal terminal and the light-emitting signal terminal are inactive level signals; When the first scanning signal end is an effective level signal, the signal of the second scanning signal end is an effective level signal, and the signals of the first reset signal end, the third reset signal end and the light-emitting signal end are invalid level signals; the voltage values of the signals of the first initial signal end, the second initial signal end and the third initial signal end are constant. In some possible implementations, in the display stage, the occurrence time of the signal of the second reset signal end being the active level signal is before the occurrence time of the signal of the first reset signal end being the active level signal, or the occurrence time of the sign