CN-117529819-B - Semiconductor device and power conversion device

CN117529819BCN 117529819 BCN117529819 BCN 117529819BCN-117529819-B

Abstract

The performance of the semiconductor device is improved. A semiconductor device is formed, which includes a semiconductor substrate having a drift layer of a first conductivity type, a body region of a second conductivity type, and JFET regions of the first conductivity type in contact with the body region on both sides of the drift layer, a plurality of trenches formed in an upper surface of the semiconductor substrate and extending in a first direction, and a gate electrode formed in the trenches and on the upper surface of the semiconductor substrate via an insulating film. In a unit cell, a first trench group including a plurality of trenches arranged in a second direction intersecting the first direction and a second trench group including a plurality of trenches arranged in the second direction are arranged in the first direction, a lower surface of a source region between adjacent trenches in the second direction has a channel region shallower than the trenches, a gate electrode includes a first portion in the plurality of trenches and a second portion located on a semiconductor substrate and connecting the first portions arranged in the first direction and the second direction to each other, and each unit cell has a plurality of JFET regions.

Inventors

SHIMIZU YUKA
SAITO TATSUNORI
MOURI TOMONORI

Assignees

株式会社日立功率半导体

Dates

Publication Date: 20260508
Application Date: 20220422
Priority Date: 20210922

Claims (9)

1.A semiconductor device, characterized in that, The device comprises: a semiconductor substrate having a drift layer of a first conductivity type; a plurality of trenches formed on an upper surface of the semiconductor substrate and extending in a first direction along the upper surface of the semiconductor substrate; a main body region of a second conductivity type different from the first conductivity type, formed on a side surface of the trench in a short side direction; a source region of the first conductivity type formed on the upper surface of the semiconductor substrate and formed within the body region; a JFET region of the first conductivity type formed on an upper surface of the drift layer, side surfaces of both sides being in contact with the body region; a drain region of the first conductivity type formed on the lower surface of the semiconductor substrate and electrically connected to the drift layer, and A gate electrode formed in the trench and on the upper surface of the semiconductor substrate via an insulating film, In the unit cell, a plurality of grooves are arranged in a second direction intersecting the first direction in a plan view to form a first groove group, a plurality of grooves are arranged in the second direction to form a second groove group, The grooves constituting the first groove group and the grooves constituting the second groove group are arranged in the first direction, The source regions are also formed between the trenches adjacent in the second direction, A channel region formed at a depth shallower than the depth of the trenches is provided at a lower surface of the source region formed between the trenches adjacent to each other in the second direction, The gate electrode includes a first portion buried in the plurality of trenches, respectively, and a second portion on the upper surface of the semiconductor substrate, connecting the first portions arranged in the first direction to each other, and connecting the first portions arranged in the second direction to each other, Each unit cell is provided with a plurality of JFET regions.
2. The semiconductor device according to claim 1, wherein, One of the JFET regions extends in the second direction directly below the first group of trenches, Another of the JFET regions extends in the second direction directly below the second set of trenches.
3. The semiconductor device according to claim 1, wherein, One of the JFET regions is formed directly under a first region between the trenches adjacent in the first direction, Another of the JFET regions is formed directly under a second region adjacent to the trench in the first direction on an opposite side of the first region.
4. The semiconductor device according to claim 1, wherein, An upper surface of a portion of the first portion of the gate electrode within the trench is lower than an upper end of the trench, Another portion of the first portion of the gate electrode within the trench is connected with the second portion of the gate electrode on the semiconductor substrate.
5. The semiconductor device according to claim 1, wherein, And a metal wiring connected to an upper surface of the gate electrode on the semiconductor substrate and extending in the second direction.
6. The semiconductor device according to claim 1, wherein, The unit cells are one of structures in which a plurality of unit cells are repeatedly arranged in the first direction without being reversed.
7. The semiconductor device according to claim 1, wherein, In the unit cell, the source region has a source region of the first trench group and a source region of the second trench group, which are separated from each other directly below a portion of the second portion of the gate electrodes that connects the first portions of the gate electrodes arranged in the first direction.
8. The semiconductor device according to claim 1, wherein, The semiconductor substrate is a semiconductor substrate including silicon carbide.
9. A power conversion device is characterized in that, Use of the semiconductor device according to claim 1.

Description

Semiconductor device and power conversion device Technical Field The present invention relates to a semiconductor device having a field effect transistor in which a channel is formed on a side surface of a semiconductor layer. Background In recent years, a MOSFET (Metal Oxide Semiconductor FIELD EFFECT Transistor) has been proposed which has a trench formed in a direction orthogonal to a source contact region formed in a stripe shape in a plan view, and a gate electrode is embedded in the trench via an insulating film. In this MOSFET, current flows through the trench sides in the depth direction. In this configuration, the on-resistance can be reduced by increasing the trench density by reducing the pitch of the trenches. For example, patent document 1 (japanese patent application laid-open No. 2004-207289) describes a MOSFET including a buried gate formed in a trench on the upper surface of a semiconductor substrate, and a channel formed on the side surface of the trench. Patent document 2 (japanese patent application laid-open No. 2021-12934) discloses a vertical MOSFET including a gate electrode extending across and directly above each of two trenches adjacent to each other in the extending direction of the trench. Prior art literature Patent literature Patent document 1 Japanese patent laid-open No. 2004-207289 Patent document 2 Japanese patent application laid-open No. 2021-12934 Disclosure of Invention Problems to be solved by the invention The MOSFET described in patent document 1 has a large gate capacitance because a plurality of trenches are formed, and has a large gate wiring resistance because gate wirings extend in a direction crossing the trenches. Therefore, there is a problem that gate delay determined by CR (capacitance×resistance) is large. In addition, since the length of the long side of the trench is determined by the design of the JFET region, it is difficult to lengthen the trench and widen the gate wiring width. In patent document 2, two trenches are included in a unit cell in the extending direction of the trenches, but the JFET region provided in the unit cell is only one, which has a problem of large on-resistance. Other objects and novel features will become apparent from the description and drawings of the specification. Means for solving the problems An outline of a representative embodiment among the embodiments disclosed in the present application will be briefly described as follows. A semiconductor device according to one embodiment includes a semiconductor substrate having a drift layer of a first conductivity type; a plurality of trenches formed on an upper surface of the semiconductor substrate and extending in a first direction along the upper surface of the semiconductor substrate; a main body region of a second conductivity type different from the first conductivity type, formed on a side surface of the trench in a short side direction; the semiconductor device includes a semiconductor substrate, a body region formed on the semiconductor substrate, a source region of a first conductivity type formed on an upper surface of the semiconductor substrate and formed in the body region, a JFET region of the first conductivity type formed on an upper surface of the drift layer, side surfaces of the body region being in contact with both sides of the body region, a drain region of the first conductivity type formed on a lower surface of the semiconductor substrate and electrically connected to the drift layer, and a gate electrode formed in the trench and on an upper surface of the semiconductor substrate via an insulating film, a plurality of trenches being arranged in a second direction intersecting the first direction in a unit cell, a plurality of trenches being arranged in the second direction in a first trench group, another portion of the plurality of trenches being arranged in the second direction in the second trench group, the trenches constituting the first trench group and the trenches constituting the second trench group being arranged in the first direction, the source region also being formed between the trenches adjacent in the second direction, the lower surface of the source region being formed between the trenches having a channel region formed at a shallower depth than the trenches, the gate electrode being provided with the first portion buried in the first direction, the semiconductor substrate being arranged on the first direction, the semiconductor substrate being connected to the first semiconductor substrate being arranged in the first direction, each unit cell is provided with a plurality of JFET regions. Effects of the invention The effects obtained by the representative embodiments of the application disclosed in the present application are briefly described below. According to the present invention, the performance of the semiconductor device can be improved. Drawings Fig. 1 is a bird's eye view showing the semiconductor device of embodiment 1. Fi