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CN-117629279-B - Data acquisition device, data acquisition method, chip and electronic equipment

CN117629279BCN 117629279 BCN117629279 BCN 117629279BCN-117629279-B

Abstract

The application discloses a data acquisition device, a data acquisition method, a chip and electronic equipment, which are applied to the chip, wherein the device comprises a sensor module which is correspondingly arranged in each processing unit of the chip, and a plurality of sensor modules are connected in sequence; the sensor module is used for receiving clock signals and data signals, carrying out data acquisition on a current processing unit, generating intermediate data signals according to acquired data and data signals, carrying out sampling processing on the intermediate data signals by using the clock signals, outputting new clock signals and new data signals, inputting the new clock signals as the clock signals into the next-stage sensor module, and inputting the new data signals as the data signals into the next-stage sensor module. The device is easy to wire and good in expandability, and delay time difference between a clock and data can be reduced, so that data acquisition is stable.

Inventors

  • SUN WEI
  • ZHU YEHUA

Assignees

  • 哲库科技(上海)有限公司

Dates

Publication Date
20260505
Application Date
20220811

Claims (14)

  1. 1. A data acquisition device is applied to a chip and is characterized by comprising a sensor module which is correspondingly arranged in each processing unit of the chip, a plurality of sensor modules are connected in sequence, The sensor module is used for receiving clock signals and data signals, collecting data of the current processing unit, generating intermediate data signals according to the collected data and the data signals, sampling the intermediate data signals by using the clock signals to output new clock signals and new data signals, and Inputting the new clock signal as a clock signal to the sensor module at the next stage, and inputting the new data signal as a data signal to the sensor module at the next stage; The last new data signal output by the sensor module comprises the acquired data of each processing unit of the chip; The sensor module comprises a sensor module, a data line and a clock line, wherein the clock line and the data line are arranged between the sensor module and the sensor module at the next stage, the clock line is used for transmitting the new clock signal output by the sensor module, the data line is used for transmitting the new data signal output by the sensor module, and the transmission distance between the clock line and the data line arranged between the sensor module and the sensor module at the next stage is the same.
  2. 2. The data acquisition device of claim 1, wherein a plurality of the sensor modules are sequentially connected in the form of a link.
  3. 3. The data acquisition device of claim 1, wherein the sensor module comprises an acquisition sensor and a trigger, wherein an input of the trigger is connected to an output of the acquisition sensor, a clock of the trigger is configured to receive the clock signal, and an output of the trigger is configured to output the new data signal; the acquisition sensor is used for acquiring data of the processing unit where the sensor module is located, so as to obtain acquisition data of the processing unit; The trigger is used for sampling the intermediate data signal by the clock signal after generating the intermediate data signal according to the acquired data and the received data signal, and outputting a new data signal, wherein the new data signal is an input data signal of the sensor module of the next stage.
  4. 4. The data acquisition device of claim 3, wherein the trigger comprises a rising edge trigger or a falling edge trigger, The trigger is used for sampling the intermediate data signal by using the rising edge of the clock signal to output the new data signal when the trigger mode is rising edge trigger, or And the trigger is used for sampling the intermediate data signal by utilizing the falling edge of the clock signal when the trigger mode is falling edge trigger and outputting the new data signal.
  5. 5. The data acquisition device of claim 3 wherein the acquisition sensor is a PVT sensor and wherein the acquisition data comprises at least one of temperature data, process data, and voltage data.
  6. 6. The data acquisition device according to any one of claims 1 to 5, wherein a combinational logic module is further arranged on a data line between the sensor module and the sensor module of the next stage, wherein an input end of the combinational logic module is connected with an output end of the sensor module, and an output end of the combinational logic module is connected with an input end of the sensor module of the next stage; The combination logic module is used for receiving the new data signals output by the sensor module, carrying out combination logic processing on the new data signals to obtain processed data signals, and taking the processed data signals as input data signals of the sensor module of the next stage.
  7. 7. The data acquisition device of claim 6, wherein a sum of a path delay time between an output of the sensor module and an input of the combinational logic module, a delay time required for the combinational logic module to perform combinational logic processing, and a path delay time between an output of the combinational logic module and an input of the sensor module at a next stage is smaller than a difference between a preset clock period and a clock setup time; The preset clock period is a clock period of the new clock signal, and the clock establishment time represents a time when the new data signal needs to reach the input end of the sensor module of the next stage in advance compared with the new clock signal.
  8. 8. The data acquisition method is characterized by being applied to a data acquisition device, wherein the data acquisition device comprises a sensor module which is correspondingly arranged in each processing unit of a chip, and a plurality of sensor modules are sequentially connected, and the method comprises the following steps: Receiving clock signals and data signals through the sensor module, carrying out data acquisition on the currently located processing unit, generating intermediate data signals according to the acquired data and the data signals, carrying out data acquisition on the data signals by utilizing the clock signals to output new clock signals and new data signals, and Inputting the new clock signal as a clock signal to the next-stage sensor module, inputting the new data signal as a data signal to the next-stage sensor module, and circularly executing the steps of receiving the clock signal and the data signal and outputting the new clock signal and the new data signal through the next-stage sensor module until the last sensor module connected in sequence outputs the new clock signal and the new data signal; The last new data signal output by the sensor module comprises the acquired data of each processing unit of the chip; The sensor module comprises a sensor module, a data line and a clock line, wherein the clock line and the data line are arranged between the sensor module and the sensor module at the next stage, the clock line is used for transmitting the new clock signal output by the sensor module, the data line is used for transmitting the new data signal output by the sensor module, and the transmission distance between the clock line and the data line arranged between the sensor module and the sensor module at the next stage is the same.
  9. 9. The method of claim 8, wherein the sensor module includes an acquisition sensor and a trigger, the data acquisition is performed on the currently located processing unit, an intermediate data signal is generated according to the acquired acquisition data and the data signal, the data acquisition is performed on the data signal by using the clock signal, and a new clock signal and a new data signal are output, including: the data acquisition is carried out on the processing unit where the sensor module is located through the acquisition sensor, so that acquisition data of the processing unit are obtained; After an intermediate data signal is generated according to the acquired data and the received data signal, the intermediate data signal is sampled and processed by the trigger through the clock signal, and a new data signal is output, wherein the new data signal is an input data signal of the sensor module of the next stage.
  10. 10. The method of claim 9, wherein the triggering of the flip-flop comprises a rising edge triggering or a falling edge triggering, wherein the sampling of the intermediate data signal by the flip-flop with the clock signal, outputting a new data signal, comprises: When the trigger mode of the trigger is rising edge trigger, sampling the intermediate data signal by the rising edge of the clock signal to output the new data signal, or And when the trigger mode of the trigger is falling edge trigger, sampling the intermediate data signal by utilizing the falling edge of the clock signal, and outputting the new data signal.
  11. 11. The method of claim 9, wherein the acquisition sensor is a PVT sensor, and wherein the acquisition data comprises at least one of temperature data, process data, and voltage data.
  12. 12. The method according to any one of claims 8 to 11, further comprising: and sequentially connecting a plurality of sensor modules in a link mode.
  13. 13. A chip comprising a plurality of processing units and a data acquisition device according to any one of claims 1 to 7.
  14. 14. An electronic device, characterized in that, the electronic device comprising the chip of claim 13.

Description

Data acquisition device, data acquisition method, chip and electronic equipment Technical Field The present application relates to the field of chip technologies, and in particular, to a data acquisition device, a data acquisition method, a chip, and an electronic device. Background With the continuous development of integrated circuit technology, the integration level of the chip is higher and higher, and the function of the chip is also stronger and stronger. In developing and designing large-scale integrated circuits, the integrated circuits are typically split into smaller modules for processing. In the process of realizing different module designs, in order to ensure the correctness of the chip functions, the time sequences of the modules are required to meet the design requirements. In the related art, a sensor is currently placed inside each module to collect data of each module inside the chip, and then each module needs to send the collected data to a centralized processing unit, and the modules are synchronized by using clock signals. However, the related art solutions still have some drawbacks, for example, as the number of sensors increases, a part of sensors needs to be transmitted over a long distance to reach the centralized processing unit, so long-distance transmission of data not only has a problem of complicated wiring, but also easily causes a problem of increased delay in the data transmission process, resulting in failure of data acquisition. Disclosure of Invention The application provides a data acquisition device, a data acquisition method, a chip and electronic equipment, which not only can reduce wiring complexity, but also can reduce delay time difference between a clock and data in a transmission process, so that data acquisition is stable, and meanwhile, the data acquisition device has better expandability. In order to achieve the above purpose, the technical scheme of the application is realized as follows: In a first aspect, an embodiment of the present application provides a data acquisition device, which is applied to a chip, where the data acquisition device includes a sensor module disposed in each processing unit of the chip, where the sensor modules are sequentially connected, and the sensor module is configured to receive a clock signal and a data signal, perform data acquisition on a current processing unit, generate an intermediate data signal according to the acquired data and data signal, perform sampling processing on the intermediate data signal by using the clock signal, output a new clock signal and a new data signal, and input the new clock signal as a clock signal to a next stage sensor module, and input the new data signal as a data signal to the next stage sensor module. In some embodiments, a plurality of sensor modules are connected in sequence by way of a link. In some embodiments, the new data signal output by the last sensor module includes the respective acquired data for each processing unit of the chip. In some embodiments, the sensor module comprises an acquisition sensor and a trigger, wherein an input end of the trigger is connected with an output end of the acquisition sensor, a clock end of the trigger is used for receiving a clock signal, an output end of the trigger is used for outputting a new data signal, the acquisition sensor is used for acquiring data of a processing unit where the sensor module is located to obtain acquisition data of the processing unit, the trigger is used for sampling the intermediate data signal by using the clock signal after generating the intermediate data signal according to the acquisition data and the received data signal to output the new data signal, and the new data signal is the input data signal of the next stage sensor module. In some embodiments, the trigger mode of the trigger comprises rising edge trigger or falling edge trigger, wherein the trigger is used for sampling the intermediate data signal by utilizing the rising edge of the clock signal to output a new data signal when the trigger mode is rising edge trigger, or used for sampling the intermediate data signal by utilizing the falling edge of the clock signal to output a new data signal when the trigger mode is falling edge trigger. In some embodiments, the acquisition sensor is a PVT sensor, wherein the acquisition data includes at least one of temperature data, process data, and voltage data. In some embodiments, a clock line and a data line are arranged between the sensor module and the next-stage sensor module, the clock line is used for transmitting a new clock signal output by the sensor module, and the data line is used for transmitting a new data signal output by the sensor module, wherein the transmission distances of the clock line and the data line arranged between the sensor module and the next-stage sensor module are the same. In some embodiments, a combination logic module is further arranged on the data line between the sensor m