CN-117712027-B - Semiconductor structure and forming method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. The method for forming the semiconductor structure comprises the steps of forming a stacked layer on a substrate, wherein the stacked layer comprises interlayer insulating layers and sacrificial layers which are alternately stacked along a first direction, the stacked layer comprises a plurality of storage areas which are arranged at intervals along a second direction, removing part of the sacrificial layers of the storage areas to form first grooves between adjacent interlayer insulating layers, forming a transistor structure in the first grooves, the transistor structure comprises a gate layer covering the inner wall of the first grooves and an active structure located in the gate layer, and forming word lines extending along the second direction, wherein the word lines cover the gate layer in the plurality of storage areas which are arranged at intervals along the second direction. The present disclosure simplifies the horizontal word line formation process, reduces the manufacturing cost of the semiconductor structure, and improves the electrical performance of the semiconductor structure.

Inventors

• Feng Daohuan

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260512

Application Date

20220905

Claims (18)

1. 1. A method of forming a semiconductor structure, comprising the steps of: Providing a substrate; Forming a stacked layer on the substrate, wherein the stacked layer comprises interlayer insulating layers and sacrificial layers which are alternately stacked along a first direction, the sacrificial layers comprise a first sacrificial layer, a second sacrificial layer and a third sacrificial layer which are sequentially stacked along the first direction, the stacked layer comprises a plurality of storage areas which are arranged at intervals along a second direction, the storage areas comprise transistor areas and bit line areas which are positioned at one side of the transistor areas along the third direction, the first direction is perpendicular to the top surface of the substrate, the second direction is parallel to the top surface of the substrate, the third direction is parallel to the top surface of the substrate, and the second direction is intersected with the third direction; etching the stacked layers to form isolation trenches between the storage regions adjacent in the second direction; forming an isolation layer filling the isolation groove; removing the stacked layer of the bit line area to form a bit line groove; removing the second sacrificial layer of the transistor region along the bit line groove, and forming a first groove between the first sacrificial layer and the third sacrificial layer in the transistor region; forming a transistor structure in the first groove, wherein the transistor structure comprises a grid electrode layer covering the inner wall of the first groove and an active structure positioned in the grid electrode layer; and forming a word line extending along the second direction, wherein the word line wraps the gate layers in the storage areas which are arranged at intervals along the second direction.
2. 2. The method of claim 1, wherein the material of the first sacrificial layer and the material of the third sacrificial layer are both oxide materials, and the material of the second sacrificial layer is a polysilicon material.
3. 3. The method of claim 1, wherein the active structure is a hollow structure, and wherein forming a transistor structure in the first trench comprises: forming the gate layer covering the inner wall of the first trench; forming a gate dielectric layer covering the inner wall of the gate layer; Forming an active structure covering the inner wall of the gate dielectric layer in the first groove, wherein the active structure comprises a channel layer, and a first active layer and a second active layer which are distributed on two opposite sides of the channel layer along a third direction; and forming an insulating filling layer which covers the inner wall of the active structure and fills the first groove.
4. 4. The method of claim 1, wherein the active structure is a solid structure, and wherein forming the transistor structure in the first trench comprises: forming the gate layer covering the inner wall of the first trench; forming a gate dielectric layer covering the inner wall of the gate layer; And forming an active structure which covers the inner wall of the gate dielectric layer and fills the first groove, wherein the active structure comprises a channel layer, and a first active layer and a second active layer which are distributed on two opposite sides of the channel layer along a third direction.
5. 5. The method of claim 3 or 4, wherein the memory region further comprises a capacitor region, the capacitor region and the bit line region being distributed on opposite sides of the transistor region along the third direction, wherein the gate layer covers an entire inner wall of the first trench, and wherein before forming the word line extending along the second direction, the method further comprises: removing the isolation layer between the capacitor region and the second active layer, exposing part of the isolation groove, and exposing the first sacrificial layer and the third sacrificial layer on the side wall of the isolation groove; removing the first sacrificial layer and the third sacrificial layer on the capacitor region and the second active layer, and removing the gate layer on the second active layer, forming a second trench in the storage region below the capacitor region and the second active layer along the first direction, and a third trench above the capacitor region and the second active layer along the first direction; and forming a first isolation layer filling the second groove, the third groove and the isolation groove between the capacitor region and the second active layer.
6. 6. The method of claim 5, further comprising, after forming a first isolation layer filling the second trench, the third trench, and the isolation trench between the capacitor region and the second active layer: Removing the second sacrificial layer of the capacitor region to form a capacitor groove between the interlayer insulating layers; Removing the gate layer exposed to the capacitor trench, exposing the second active layer; And forming a capacitor structure electrically connected with the second active layer in the capacitor groove.
7. 7. The method of forming a semiconductor structure according to claim 3 or 4, wherein the forming a word line extending in the second direction comprises: Removing the isolation layer between the channel layer and the first active layer, exposing part of the isolation groove, and exposing the first sacrificial layer and the third sacrificial layer on the side wall of the isolation groove; Removing the first sacrificial layer and the third sacrificial layer on the channel layer and the first active layer, and forming a fourth trench located below the channel layer and the first active layer in the first direction and a fifth trench located above the channel layer and the first active layer in the first direction in the storage region; Removing the gate layer on the first active layer along the fourth trench and the fifth trench; And depositing a word line material along the fourth groove and the fifth groove to form the word line which extends along the second direction and covers a plurality of gate layers which are arranged at intervals along the second direction.
8. 8. The method of forming a semiconductor structure of claim 7, wherein depositing a wordline material along the fourth trench and the fifth trench comprises: And depositing a word line material along the fourth groove and the fifth groove by adopting a selective atomic layer deposition process, wherein the deposition rate of the word line material on the surface of the gate layer is larger than that of the word line material on the interlayer insulating layer, and the word line material at least fills the fourth groove above the channel layer and the fifth groove below the channel layer.
9. 9. The method of claim 8, wherein the gate layer is made of titanium nitride, the word line is made of molybdenum metal, the interlayer insulating layer is made of nitride, and the process strip for depositing the word line comprises using molybdenum dichloride MoO2Cl2 or molybdenum pentachloride MoCl5 as a precursor material and using ammonia gas or hydrogen gas as an auxiliary reaction gas, wherein the reaction temperature is 450-600 ℃.
10. 10. The method of forming a semiconductor structure of claim 8, further comprising, after forming a word line extending in the second direction, the steps of: Forming a second isolation layer, wherein the second isolation layer is positioned in the fourth groove below the first active layer, the fifth groove above the second active layer and the isolation groove between the channel layer and the first active layer; And forming a bit line extending along the first direction in the bit line groove, wherein the bit line is electrically connected with the first active layer of the transistor structure.
11. 11. The method of claim 1, wherein the material of the active structure is an oxide semiconductor material.
12. 12. A semiconductor structure, comprising: A substrate; A stacked structure on the substrate, wherein the stacked structure comprises a plurality of memory cells arranged at intervals along a first direction and a second direction and an interlayer insulating layer positioned between adjacent memory cells along the first direction, the memory cells comprise a transistor structure, the transistor structure comprises an active structure and a grid layer distributed around the periphery of the active structure, and the active structure is a hollow structure; the active structure comprises a channel layer, and a first active layer and a second active layer which are positioned on two opposite sides of the channel layer along a third direction, wherein the first direction is perpendicular to the top surface of the substrate, the second direction is parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate; and the word line extends along the second direction and coats the gate layers in the memory cells which are arranged at intervals along the second direction.
13. 13. The semiconductor structure of claim 12, wherein the transistor structure further comprises: And the active structures are distributed around the periphery of the insulating filling layer.
14. 14. The semiconductor structure of claim 13, wherein a thickness of the insulating fill layer is greater than or equal to a thickness of the channel layer in the first direction.
15. 15. The semiconductor structure of claim 12, wherein the material of the gate layer is titanium nitride, the material of the word line is metallic molybdenum, and the material of the interlayer insulating layer is a nitride material.
16. 16. The semiconductor structure of claim 13, wherein the memory cell further comprises a capacitance structure located outside the transistor structure along the third direction, the capacitance structure comprising: the lower electrode layer comprises a main body part and an extension part connected with the main body part along the third direction, the extension part covers the top surface of the second active layer and the bottom surface of the second active layer, the main body part covers the side surface of the second active layer, and the top surface of the second active layer and the bottom surface of the second active layer are distributed at two opposite ends of the second active layer along the first direction; A dielectric layer covering the surface of the lower electrode layer; and the upper electrode layer is covered on the surface of the dielectric layer.
17. 17. The semiconductor structure of claim 12, wherein a thickness of the word line on a top surface of the gate layer or on a bottom surface of the gate layer is greater than or equal to a thickness of the gate layer in the first direction.
18. 18. The semiconductor structure of claim 12, wherein the material of the active structure is an oxide semiconductor material.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic devices such as computers, and is composed of a plurality of memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected with a word line, the source is electrically connected with a bit line, and the drain is electrically connected with a capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that data information stored in the capacitor can be read or written into the capacitor through the bit line. In order to meet the demands of the semiconductor structures such as DRAMs that are increasingly miniaturized in size and have increasingly improved data storage capabilities, semiconductor structures such as DRAMs having three-dimensional structures have been developed. In the fabrication of semiconductor structures such as DRAMs having a three-dimensional structure, a main method is to form stacked layers by an epitaxial process, and then process the stacked layers to form a three-dimensional stacked structure. However, the epitaxial growth method is complex in process and is prone to generating defects such as stress in the stacked layers, so that the manufacturing cost of the semiconductor structure is increased, and the performance and the manufacturing yield of the semiconductor structure are reduced. Therefore, how to simplify the manufacturing process of the semiconductor structure, reduce the manufacturing cost of the semiconductor structure, and improve the performance and the manufacturing yield of the semiconductor structure is a technical problem to be solved currently. Disclosure of Invention The semiconductor structure and the forming method thereof provided by some embodiments of the present disclosure are used for simplifying the manufacturing process of the semiconductor structure, reducing the manufacturing cost of the semiconductor structure, and improving the performance and the manufacturing yield of the semiconductor structure. According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, including the steps of: Forming a stacked layer on a substrate, wherein the stacked layer comprises interlayer insulating layers and sacrificial layers which are alternately stacked along a first direction, the stacked layer comprises a plurality of storage areas which are arranged at intervals along a second direction, the first direction is perpendicular to the top surface of the substrate, and the second direction is parallel to the top surface of the substrate; removing part of the sacrificial layer of the storage area to form a first groove between adjacent interlayer insulating layers; forming a transistor structure in the first groove, wherein the transistor structure comprises a grid electrode layer covering the inner wall of the first groove and an active structure positioned in the grid electrode layer; and forming a word line extending along the second direction, wherein the word line wraps the gate layers in the storage areas which are arranged at intervals along the second direction. In some embodiments, the step of forming a stack of layers on the substrate comprises: Providing a substrate; The interlayer insulating layer and the sacrificial layer are alternately deposited on the top surface of the substrate along the first direction, and the sacrificial layer comprises a first sacrificial layer, a second sacrificial layer and a third sacrificial layer which are sequentially stacked along the first direction. In some embodiments, the material of the first sacrificial layer and the material of the third sacrificial layer are both oxide materials, and the material of the second sacrificial layer is a polysilicon material. In some embodiments, before forming the first trench between adjacent interlayer insulating layers, the method further includes: etching the stacked layers to form isolation trenches between the storage regions adjacent in the second direction; and forming an isolation layer filling the isolation groove. In some embodiments, the memory region includes a transistor region and a bit line region located at one side of the transistor region along a third direction, wherein the third direction is parallel to a top surface of the substrate and the second direction intersects the third direction, and the step of forming a first trench located between adjacent interlayer insulating layers includes: removing the stacked layer of the bit line area to form a bit line groove; and removing the second sacrificial layer of the transistor region along the bit line