CN-117758217-B - Through silicon via capable of inhibiting copper extrusion and preparation method thereof
Abstract
The invention discloses a through silicon via capable of inhibiting copper extrusion and a preparation method thereof, wherein a ZrW 2‑x Mo x O 8 film with a certain thickness is deposited at the bottom of a TSV by using magnetron sputtering, then after copper with a certain thickness is electroplated, the steps are repeated, a plurality of layers of ZrW 2‑x Mo x O 8 films are deposited in the middle of Cu, zrW 2‑x Mo x O 8 is a material with a negative thermal expansion coefficient, the thermal expansion coefficient is-4.3 multiplied by 10 ‑6 to-7.7 multiplied by 10 ‑6 K ‑1 , the material is contracted rather than expanded when being heated, cu in the through silicon via is contracted rather than expanded during the heat treatment (such as annealing) or temperature cycle of the through silicon via, and the ZrW 2‑x Mo x O 8 material is contracted rather than expanded, so that the heat induction stress caused by the mismatch of the thermal expansion coefficients among the materials forming the through silicon via can be partially counteracted. Thus, the inventive method of fabricating through silicon vias can improve the reliability of copper filled TSVs while allowing for optimized device performance (e.g., allowing for higher temperature annealing of copper).
Inventors
- CHEN ZHIWEN
- DU SONG
- LIU LI
- LIU SHENG
Assignees
- 珠海深圳清华大学研究院创新中心
Dates
- Publication Date
- 20260505
- Application Date
- 20231206
Claims (10)
- 1. The preparation method of the through silicon via capable of inhibiting copper extrusion is characterized by comprising the following preparation steps: S1, preparing a precursor by using zirconyl nitrate, ammonium tungstate and ammonium molybdate as raw materials and adopting a coprecipitation method; S2, sintering and annealing the precursor to obtain a ZrW 2-x Mo x O 8 target; S3, pre-sputtering the ZrW 2-x Mo x O 8 target; S4, depositing a film on the bottom of the silicon through hole of the silicon substrate subjected to degreasing and rust removal pretreatment by using the ZrW 2-x Mo x O 8 target material subjected to pre-sputtering in the S3 and using a radio frequency magnetron sputtering technology; the silicon substrate is provided with a silicon through hole and a groove communicated with the silicon through hole, and the groove is arranged on the surface of the silicon substrate; S5, cleaning and drying the silicon through holes treated in the step S4; s6, carrying out copper electroplating treatment on the silicon through hole treated in the S5; s7, repeating the steps S3-S6 at least once until the metal layer fills the silicon through hole; And S8, cleaning and drying the through silicon via prepared in the step S7 to finally obtain the through silicon via capable of inhibiting copper extrusion.
- 2. The method for preparing a through silicon via capable of inhibiting copper extrusion according to claim 1, wherein zirconyl nitrate, ammonium tungstate and ammonium molybdate in S1 are used as raw materials, and the molar ratio of the zirconyl nitrate, the ammonium tungstate and the ammonium molybdate is 1 (2-x): x,0< x <2.
- 3. The method for preparing the through silicon via capable of inhibiting copper extrusion according to claim 2, wherein the step of preparing the precursor by the S1 coprecipitation method is characterized in that zirconyl nitrate, ammonium tungstate and ammonium molybdate are respectively dissolved in deionized water, the zirconyl nitrate solution is magnetically stirred, ammonium tungstate and ammonium molybdate aqueous solution are simultaneously added, stirring is carried out for 2-3 hours, drying and grinding are carried out to obtain powder, the powder is placed into a muffle furnace, the muffle furnace is kept at 500-800 ℃ for 4-8 hours and then taken out, and a target material with phi 60mm multiplied by 5mm to phi 60mm multiplied by 4mm is pressed on a hydraulic press to obtain the precursor.
- 4. The method for preparing the through silicon via capable of inhibiting copper extrusion as claimed in claim 1, wherein the specific operation step of sintering and annealing the precursor in the step S2 comprises the steps of placing the precursor in a high-temperature furnace, sintering for 5-8h at 900-1200 ℃, and then quenching in ice water to obtain the ZrW 2-x Mo x O 8 target.
- 5. The method for preparing a through silicon via capable of inhibiting copper extrusion as recited in claim 1, wherein the degreasing and rust removal pretreatment in S4 comprises immersing a silicon substrate in an alkaline solution, removing surface oil stains, then rinsing the sample surface with deionized water, then immersing the silicon substrate in an acidic solution, removing surface oxide layers, and then rinsing the sample surface with deionized water.
- 6. The method for preparing the through silicon via capable of inhibiting copper extrusion according to claim 1, wherein the specific operation parameters of depositing a film on the bottom of the through silicon via of the silicon substrate subjected to degreasing and rust removal pretreatment in the step S4 by using a radio frequency magnetron sputtering technology are that the background vacuum degree is 2×10 -3 -2.2×10 -3 Pa, the sputtering power is 200-220W, the ratio of the inflow amount of argon and oxygen serving as working gases is 24:12, the working air pressure is 2.0-2.5Pa, the substrate-target distance is 40-45mm, the deposition time is 6-8h, and the radio frequency magnetron sputtering process comprises bias cleaning, film deposition and film annealing.
- 7. The method for preparing a through silicon via capable of suppressing copper extrusion as recited in claim 1, wherein the step of electroplating in S6 comprises the steps of placing a through silicon via sample into an electroplating solution for electroplating, adding an additive to the electroplating solution, wherein the additive comprises an inhibitor, an accelerator and a leveling agent, the electroplating is performed under water bath heating at 40-50 ℃ and a current density of 3-5 mA/cm2, electroplating 1-2 h to form a metal layer, the metal layer does not fill the through silicon via, and performing ultrasonic cleaning on the electroplated through silicon via sample and then drying.
- 8. The method of claim 7, wherein the plating solution is copper methylsulfonate, methylsulfonic acid, hydrochloric acid, and the additives include an inhibitor UPT3360S, an accelerator UPT3360A, and a leveler UPT3360L.
- 9. The method for preparing a through silicon via capable of inhibiting copper extrusion as claimed in any one of claims 1 to 8, wherein the step of cleaning and drying in S8 comprises the steps of ultrasonically cleaning the through silicon via sample prepared in S7 in alcohol, ultrasonically cleaning with deionized water, and then performing drying treatment to finally obtain the through silicon via capable of inhibiting copper extrusion.
- 10. The through silicon via capable of suppressing copper extrusion prepared by the method for preparing a through silicon via capable of suppressing copper extrusion as claimed in any one of claims 1 to 9.
Description
Through silicon via capable of inhibiting copper extrusion and preparation method thereof Technical Field The invention belongs to the field of electronic packaging, and particularly relates to a through silicon via capable of inhibiting copper extrusion and a preparation method thereof. According to the through silicon via method, cu and a material with a negative expansion coefficient are filled in the TSV, so that the extrusion of TSV copper is inhibited. Background In recent years, integrated circuit chips are increasingly miniaturized, and the requirements for packaging are also increasing. With the increasing packaging density, two-dimensional packaging has reached a limit. Three-dimensional packaging technology is the best solution to extend moore's law. Currently, three-dimensional packaging is implemented mainly using through silicon vias (Though silicon vias, TSVs) or multi-chip stacks. Among them, the three-dimensional packaging technology based on through-silicon via interconnection is the most promising packaging technology in three-dimensional packaging due to unique advantages. The TSVs are formed by directly etching through holes in the chips and then filling conductive materials into the through holes to realize electrical signal exchange between the chips. As a key component in three-dimensional electronic packages, TSV structures may enable vertical interconnection of stacked chips. Compared with the traditional packaging mode, the TSV packaging technology has many advantages, such as short interconnection path, small packaging area, high bandwidth, higher packaging density and the like. However, the material composition and the internal structure of TSV are complex, and are typical heterogeneous units, and the thermal expansion coefficients of the internal materials are greatly different. Under thermal loading, thermal mismatch between TSV interior materials can lead to serious reliability problems such as, but not limited to, (1) substrate cracking, (2) interfacial delamination, and (3) transistor performance degradation. Copper extrusion is one of the typical failure modes, and TSVs undergo continuous temperature changes during service, and thermal stresses are generated internally due to the large difference in thermal expansion coefficients of copper and silicon and the difference in expansion or contraction degrees of copper and silicon during temperature changes. When the thermal stress exceeds the yield strength of copper, the copper is plastically deformed and even creep occurs, resulting in extrusion of copper. Extrusion of copper can deform nearby structures, resulting in device failure. Currently, solutions to this problem have been mainly to add buffers and use special structures. However, none of the existing schemes and techniques for inhibiting copper extrusion in TSVs are mature. Therefore, a need exists to develop a complete method of inhibiting copper expansion in TSVs. Disclosure of Invention In view of this, an object of the present invention is to provide a through silicon via and a method of manufacturing the same capable of suppressing copper extrusion by filling the inside of the TSV with Cu and a material of negative expansion coefficient, thereby suppressing TSV copper extrusion. Specifically, the invention provides a preparation method of a through silicon via capable of inhibiting copper extrusion, which comprises the following preparation steps: S1, preparing a precursor by using zirconyl nitrate, ammonium tungstate and ammonium molybdate as raw materials and adopting a coprecipitation method; S2, sintering and annealing the precursor to obtain a ZrW 2-xMoxO8 target; s3, pre-sputtering the ZrW 2-xMoxO8 target; S4, depositing a film on the bottom of the silicon through hole of the silicon substrate subjected to degreasing and rust removal pretreatment by using the ZrW 2-xMoxO8 target material subjected to pre-sputtering in the S3 and using a radio frequency magnetron sputtering technology; the silicon substrate is provided with a silicon through hole and a groove communicated with the silicon through hole, and the groove is arranged on the surface of the silicon substrate; S5, cleaning and drying the silicon through holes treated in the step S4; s6, carrying out copper electroplating treatment on the silicon through hole treated in the S5; s7, repeating the steps S3-S6 at least once until the metal layer fills the silicon through hole; And S8, cleaning and drying the through silicon via prepared in the step S7 to finally obtain the through silicon via capable of inhibiting copper extrusion. In some specific embodiments of the invention, the molar ratio of the zirconyl nitrate, the ammonium tungstate and the ammonium molybdate in the S1 is 1 (2-x): x,0< x is less than or equal to 2. In some specific embodiments of the invention, the step of preparing the precursor by the S1 coprecipitation method comprises the steps of respectively dissolving zirconyl nitrate,