CN-117765999-B - Command decoding circuit and method thereof and semiconductor memory

Abstract

The embodiment of the disclosure provides a command decoding circuit, a method thereof and a semiconductor memory, wherein the command decoding circuit comprises a clock processing module, a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, wherein the clock processing module is configured to receive an initial clock signal, perform frequency division and phase separation on the initial clock signal and output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; the command sampling module is configured to receive a command address signal, sample the command address signal by using a first clock signal, a second clock signal, a third clock signal and a fourth clock signal respectively, and output a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; and the decoding module is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal and output a target decoding signal. The embodiment of the disclosure can realize correct decoding of the command signal.

Inventors

• GAO ENPENG

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20220919

Claims (14)

1. 1. A command decoding circuit, the command decoding circuit comprising: The clock processing module is configured to receive an initial clock signal, perform frequency division and phase separation processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are a group of signals with the same clock cycle and different phases by 90 degrees in sequence, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock cycle of the first clock signal is 2 times that of the initial clock signal; the command sampling module is connected with the clock processing module and is configured to receive a command address signal, and is used for respectively sampling the command address signal by utilizing the first clock signal, the second clock signal, the third clock signal and the fourth clock signal and outputting a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; the decoding module is connected with the clock processing module and the command sampling module and is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal and output a target decoding signal; the command address signal, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal all comprise N-bit sub-signals, and the command sampling module comprises N command sampling units; The ith command sampling unit is connected with the clock processing module and is configured to delay the ith sub-signal of the command address signal to obtain a signal to be processed, sample the signal to be processed by using the first clock signal and output the ith sub-signal of the first sampling signal, sample the signal to be processed by using the second clock signal and output the ith sub-signal of the second sampling signal, sample the signal to be processed by using the third clock signal and output the ith sub-signal of the third sampling signal and sample the signal to be processed by using the fourth clock signal and output the ith sub-signal of the fourth sampling signal, Wherein i and N are positive integers, and i is less than or equal to N.
2. 2. The command decoding circuit of claim 1, wherein a rising edge of the first clock signal is aligned with a rising edge of the initial clock signal at an odd clock cycle, a rising edge of the second clock signal is aligned with a falling edge of the initial clock signal at an odd clock cycle, a rising edge of the third clock signal is aligned with a rising edge of the initial clock signal at an even clock cycle, and a rising edge of the fourth clock signal is aligned with a falling edge of the initial clock signal at an even clock cycle.
3. 3. The command decoding circuit of any one of claims 1-2, wherein the command decoding circuit further comprises: the chip selection sampling module is connected with the clock processing module and is configured to receive a chip selection signal, sample the chip selection signal by utilizing the first clock signal and the third clock signal respectively, and output a first chip selection sampling signal and a second chip selection sampling signal; wherein the chip select signal is used to indicate whether the command address signal is valid or invalid.
4. 4. The command decoding circuit of claim 1 wherein the ith command sample cell comprises a first delay cell, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop, wherein, The input end of the first delay unit receives an ith sub-signal of the command address signal, and the output end of the first delay unit outputs the signal to be processed; The input end of the first trigger receives the signal to be processed, the clock end of the first trigger receives the first clock signal, and the output end of the first trigger outputs an ith sub-signal of the first sampling signal; The input end of the second trigger receives the signal to be processed, the clock end of the second trigger receives the second clock signal, and the output end of the second trigger outputs an ith sub-signal of the second sampling signal; The input end of the third trigger receives the signal to be processed, the clock end of the third trigger receives the third clock signal, and the output end of the third trigger outputs an ith sub-signal of the third sampling signal; The input end of the fourth trigger receives the signal to be processed, the clock end of the fourth trigger receives the fourth clock signal, and the output end of the fourth trigger outputs an ith sub-signal of the fourth sampling signal.
5. 5. The command decoding circuit of claim 1, wherein the decoding module comprises: the second delay unit is connected with the clock processing module and is configured to receive the first clock signal, delay the first clock signal and output a first delayed clock signal; The third delay unit is connected with the clock processing module and is configured to receive the third clock signal, delay the third clock signal and output a third delayed clock signal; The decoding processing unit is connected with the command sampling module, the second delay unit and the third delay unit and is configured to decode and sample the N-bit sub-signal of the first sampling signal and the N-bit sub-signal of the second sampling signal based on the third delay clock signal and output a first decoding signal; The first decoding signal and the second decoding signal form the target decoding signal, the first decoding signal indicates the content of the command address signal in the 1 st initial clock period, the second decoding signal indicates the content of the command address signal in the 2 nd initial clock period, and the initial clock period refers to the clock period of the initial clock signal.
6. 6. The command decoding circuit of claim 5, wherein the decoding processing unit comprises: The first decoding unit is connected with the command sampling module and the third delay unit and is configured to perform logic operation on the N-bit sub-signal of the first sampling signal and the N-bit sub-signal of the second sampling signal and output a first intermediate signal; the second decoding unit is connected with the command sampling module and the second delay unit and is configured to perform logic operation on the N-bit sub-signal of the third sampling signal and the N-bit sub-signal of the fourth sampling signal to output a second intermediate signal, and the first delay clock signal is utilized to perform sampling processing on the second intermediate signal to output the second decoding signal.
7. 7. The command decoding circuit of claim 6, wherein N=4, the first decoding unit comprises a first logic unit and a fifth flip-flop, wherein, The input end of the first logic unit receives the 4-bit sub-signal of the first sampling signal and the 4-bit sub-signal of the second sampling signal, the output end of the first logic unit outputs a first intermediate signal, the input end of the fifth trigger receives the first intermediate signal, the clock end of the fifth trigger receives the third delay clock signal, and the output end of the fifth trigger outputs the first decoding signal.
8. 8. The command decoding circuit of claim 6, wherein N = 4, the second decoding unit includes a second logic unit and a sixth flip-flop; The input end of the second logic unit receives the 4-bit sub-signal of the third sampling signal and the 4-bit sub-signal of the fourth sampling signal, the output end of the second logic unit outputs a second intermediate signal, the input end of the sixth trigger receives the second intermediate signal, the clock end of the sixth trigger receives the first delay clock signal, and the output end of the sixth trigger outputs the second decoding signal.
9. 9. The command decoding circuit of claim 3, wherein the chip select sampling module comprises a fourth delay unit, a seventh flip-flop, and an eighth flip-flop, wherein, The input end of the fourth delay unit receives the chip selection signal, and the output end of the fourth delay unit outputs a chip selection delay signal; The input end of the seventh trigger receives the chip selection delay signal, the clock end of the seventh trigger receives the first clock signal, and the output end of the seventh trigger outputs the first chip selection sampling signal; the input end of the eighth trigger receives the chip selection delay signal, the clock end of the eighth trigger receives the third clock signal, and the output end of the eighth trigger outputs the second chip selection sampling signal.
10. 10. A method of command decoding, the method comprising: The method comprises the steps of carrying out frequency division and phase separation on an initial clock signal and outputting a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are a group of signals with the same clock period and sequentially different in phase by 90 degrees, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is 2 times of the clock period of the initial clock signal; sampling command address signals by using the first clock signal, the second clock signal, the third clock signal and the fourth clock signal respectively, and outputting a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; Decoding and sampling the first, second, third and fourth sampling signals based on the first and third clock signals, and outputting a target decoded signal; The command address signal, the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal each comprise an N-bit sub-signal; The method comprises the steps of obtaining a command address signal, carrying out delay processing on an ith sub-signal of the command address signal to obtain a signal to be processed, carrying out sampling processing on the signal to be processed by utilizing the first clock signal to output the ith sub-signal of the first sampling signal, carrying out sampling processing on the signal to be processed by utilizing the second clock signal to output the ith sub-signal of the second sampling signal, carrying out sampling processing on the signal to be processed by utilizing the third clock signal to output the ith sub-signal of the third sampling signal, carrying out sampling processing on the signal to be processed by utilizing the fourth clock signal to output the ith sub-signal of the fourth sampling signal, Wherein i and N are positive integers, and i is less than or equal to N.
11. 11. The command decoding method of claim 10, wherein a rising edge of the first clock signal is aligned with a rising edge of the initial clock signal in an odd period, a rising edge of the second clock signal is aligned with a falling edge of the initial clock signal in an odd period, a rising edge of the third clock signal is aligned with a rising edge of the initial clock signal in an even period, and a rising edge of the fourth clock signal is aligned with a falling edge of the initial clock signal in an even period.
12. 12. The command decoding method of claim 11, wherein the method further comprises: Sampling the chip selection signal by using the first clock signal and the third clock signal respectively, and outputting a first chip selection sampling signal and a second chip selection sampling signal; wherein the chip select signal is used to indicate whether the command address signal is valid or invalid.
13. 13. A semiconductor memory comprising the command decoding circuit according to any one of claims 1 to 10.
14. 14. The semiconductor memory of claim 13, wherein the semiconductor memory is a dynamic random access memory DRAM and the semiconductor memory meets LPDDR6 memory specifications.

Description

Command decoding circuit and method thereof and semiconductor memory Technical Field The present disclosure relates to the field of integrated circuits, and more particularly, to a command decoding circuit, a method thereof, and a semiconductor memory. Background With the continuous development of semiconductor technology, the design principle and working details of the memory are updated, and various circuits in the memory need to be improved according to new requirements so as to meet the design requirements and achieve better memory performance. Disclosure of Invention The present disclosure provides a command decoding circuit, a method thereof, and a semiconductor memory capable of achieving correct decoding of command address signals. In a first aspect, embodiments of the present disclosure provide a command decoding circuit, the command decoding circuit comprising: The clock processing module is configured to receive an initial clock signal, perform frequency division and phase separation processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are a group of signals with the same clock cycle and different phases by 90 degrees in sequence, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock cycle of the first clock signal is 2 times that of the initial clock signal; the command sampling module is connected with the clock processing module and is configured to receive a command address signal, and is used for respectively sampling the command address signal by utilizing the first clock signal, the second clock signal, the third clock signal and the fourth clock signal and outputting a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; And the decoding module is connected with the clock processing module and the command sampling module and is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal and output a target decoding signal. In some embodiments, a rising edge of the first clock signal is aligned with a rising edge of the initial clock signal at an odd clock period, a rising edge of the second clock signal is aligned with a falling edge of the initial clock signal at an odd clock period, a rising edge of the third clock signal is aligned with a rising edge of the initial clock signal at an even clock period, and a rising edge of the fourth clock signal is aligned with a falling edge of the initial clock signal at an even clock period. In some embodiments, the command decoding circuit further comprises a chip selection sampling module connected with the clock processing module and configured to receive a chip selection signal, sample the chip selection signal by using the first clock signal and the third clock signal respectively, and output a first chip selection sampling signal and a second chip selection sampling signal, wherein the chip selection signal is used for indicating whether the command address signal is valid or invalid. In some embodiments, the command address signal, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal each include N-bit sub-signals, the command sampling module includes N command sampling units, an ith command sampling unit connected with the clock processing module and configured to delay the ith sub-signal of the command address signal to obtain a signal to be processed, sample the signal to be processed with the first clock signal, output the ith sub-signal of the first sampling signal, sample the signal to be processed with the second clock signal, output the ith sub-signal of the second sampling signal, sample the signal to be processed with the third clock signal, output the ith sub-signal of the third sampling signal, sample the signal to be processed with the fourth clock signal, and output the ith sub-signal of the fourth sampling signal, wherein i and N are integers equal to or less than N. In some embodiments, the ith command sampling unit comprises a first delay unit, a first trigger, a second trigger, a third trigger and a fourth trigger, wherein the input end of the first delay unit receives an ith sub-signal of the command address signal, the output end of the first delay unit outputs the signal to be processed, the input end of the first trigger receives the signal to be processed, the clock end of the first trigger receives the first clock signal, the output end of the first trigger outputs the ith sub-signal of the first sampling signal, the input end of the second trigger receives the signal to be processed, the clock end of the second t