CN-117769738-B - Backboard and method for pulse width modulation

Abstract

A backplane for driving a display includes a two-dimensional array of pixel drive circuits organized into rows and columns. The backplane has at least one shift register addressing component comprising a shift register chain formed of a plurality of control shift registers connected in series with and separated by equally sized groups of non-control shift registers. Each control shift register controls a different one of a plurality of word lines, each word line being connected to a pixel driving circuit of a row. The back plate further includes a plurality of bit lines, each bit line being connected to a column of pixel driving circuits. The shift register data sequence is input to a first control shift register of the plurality of control shift registers and propagates through the shift register chain to control the plurality of word lines to load display values from the bit lines into the pixel drive circuits.

Inventors

• JEFFREY LEE
• LAW ROBERT

Assignees

• 谷歌有限责任公司

Dates

Publication Date

20260508

Application Date

20220714

Priority Date

20210714

Claims (18)

1. 1. A backplate configured to drive a display, the backplate comprising: A pixel drive circuit array organized into a plurality of rows and a plurality of columns, the pixel drive circuit array comprising a memory circuit; A plurality of word lines; A plurality of bit lines, and At least one shift register addressing component, the at least one shift register addressing component comprising: a plurality of control shift registers, the plurality of control shift registers having an output operable to control at least one word line of the plurality of word lines; A plurality of non-control shift registers connected in series with the plurality of control shift registers to form a shift register chain, wherein a group of at least one of the plurality of non-control shift registers is logically located between sequential ones of the plurality of control shift registers, and A sequence input of a first control shift register of the plurality of control shift registers is for receiving a shift register data sequence that in operation controls non-contiguous selection for the plurality of word lines, wherein the shift register data sequence comprises a plurality of write pointers.
2. 2. The backplane of claim 1, wherein a first number of non-controlled shift registers in any one group is equal to a second number of non-controlled shift registers in any other group.
3. 3. The backplane of claim 1, wherein a first number of pixel drive circuits on one of the rows operable by a first one of the plurality of word lines is the same as a second number of pixel drive circuits on any other one of the plurality of word lines operable by the word lines.
4. 4. The backplane of claim 1, wherein pixel drive circuits of each row operable by all word lines controllable by a shift register of a same shift register addressing component are arranged across all of the plurality of columns of the array.
5. 5. The backplane of claim 1, wherein the plurality of word lines are configured to drive even rows of the display, the backplane further comprising: A second shift register addressing component, the second shift register addressing component comprising: a plurality of control shift registers, each of the plurality of control shift registers having an output operable to control a different one of a plurality of word lines of the display to drive an odd numbered row of the display; A plurality of non-control shift registers connected in series with the plurality of control shift registers to form a shift register chain, wherein a group of at least one of the plurality of non-control shift registers is logically located between sequential ones of the plurality of control shift registers, and A sequence input of a first control shift register of the plurality of control shift registers is for receiving a shift register data sequence operable to control selection of the plurality of word lines.
6. 6. The back plate of claim 1, wherein, in operation: Selectively enabling a memory circuit of each of the pixel drive circuits corresponding to at least a portion of one of the plurality of rows to receive a display value presented by a respective bit line of the memory circuit by an action of one of the plurality of word lines controlled by one of the plurality of control shift registers; Each pixel drive circuit is operable to generate an output operable to drive a display element of the display in accordance with the display value stored in the respective memory circuit; the first shift register of each shift register addressing assembly being operable to receive a data value from the sequence input, and The data value propagates through the shift register chain on successive cycles of a clock.
7. 7. The backplane of claim 6, wherein, in operation, the respective display values stored in the respective memory circuits in the array of pixel drive circuits are a single bit such that a logic 1 stored in each memory circuit places the corresponding pixel drive circuit in an on state and a logic 0 stored in the memory circuit places the corresponding pixel drive circuit in an off state.
8. 8. The backplane of claim 6, wherein, in operation, the respective display values stored in the respective memory circuits are analog values.
9. 9. The backplane of claim 6, wherein, in operation, the data values received by the first one of the plurality of control shift registers are arranged in a predetermined sequence that does not cause more than one row to enable respective memory circuits of corresponding pixel drive circuits on the row to receive display values and store display values as the data values propagate through the shift register chain.
10. 10. A method of operating a two-dimensional display of display elements, the method comprising: providing a backplane that drives the two-dimensional display, the backplane comprising: a two-dimensional array of pixel drive circuits organized into a plurality of rows and a plurality of columns, the array of pixel drive circuits: comprising corresponding memory circuits, and In operation, an output can be generated from the respective display values stored in the corresponding memory circuits, the output driving a display element of the two-dimensional display; A plurality of word lines; A plurality of bit lines, and A shift register addressing assembly comprising: A plurality of control shift registers, each of the plurality of control shift registers being operable to control at least one of the plurality of word lines in accordance with a respective data value in the corresponding control shift register, wherein, in operation, a respective memory circuit of the plurality of pixel drive circuits corresponding to at least a portion of one of the plurality of rows is selectively enabled by an action of one of the plurality of word lines to receive a display value of a respective display value presented by a respective bit line of the respective memory circuit, and A plurality of non-control shift registers, the plurality of non-control shift registers being inoperable to control any word line of the plurality of word lines, wherein the plurality of control shift registers and the plurality of non-control shift registers are connected in series in a shift register chain, wherein a group of one or more of the plurality of non-control shift registers is logically disposed within the shift register chain, between consecutive ones of the plurality of control shift registers, such that the respective data value propagates through both the plurality of control shift registers and the plurality of non-control shift registers in response to consecutive cycles of a clock signal; the method further comprises: Inputting a data value from a shift register data sequence to a first control shift register of the plurality of control shift registers at each cycle of the clock signal, the shift register data sequence comprising a plurality of write pointers, wherein the shift register data sequence is arranged such that a maximum value of one control shift register of the plurality of control shift registers operates its respective word line during any one period of the clock signal, wherein the shift register data sequence comprises a plurality of write pointers, and Successive periods of the clock signal are provided to the plurality of control shift registers and the plurality of non-control shift registers to propagate the respective data values through the shift register chain.
11. 11. The method of claim 10, wherein a first number of uncontrolled shift registers in any one group is equal to a second number of uncontrolled shift registers in any other group.
12. 12. The method of claim 10, wherein a first number of pixel drive circuits on one of the plurality of rows operated by a first one of the plurality of word lines controlled by one of the plurality of control shift registers is the same as a second number of pixel drive circuits on any other one of the plurality of word lines operated by other shift registers of the same shift register addressing component.
13. 13. The method of claim 10, wherein the pixel drive circuits of each row operated by all of the plurality of word lines controlled by the shift register of the same shift register addressing component are arranged across all columns of the two-dimensional array of pixel drive circuits.
14. 14. The method of claim 10, wherein, in operation: Selectively enabling respective memory circuits of the pixel drive circuits corresponding to at least a portion of one of the plurality of rows to receive a display value of the respective display values presented by the respective bit lines of the respective memory circuits by an action of one of the plurality of word lines controlled by one of the plurality of control shift registers; Each pixel drive circuit generates an output operable to drive the display element of the two-dimensional display in accordance with the respective display value stored in the corresponding memory circuit; the first shift register of each shift register addressing component is operable to receive the respective data value from the sequence input, and The respective data values propagate through the shift register chain on successive cycles of a clock.
15. 15. The method of claim 14, wherein in operation, the respective display values stored in the respective memory circuits are a single bit such that a logic 1 stored in each memory circuit places a corresponding pixel drive circuit in an on state and a logic 0 stored in each memory circuit places the corresponding pixel drive circuit in an off state.
16. 16. The method of claim 14, wherein, in operation, the respective display values stored in the respective memory circuits are analog values.
17. 17. The method of claim 14, wherein, in operation, data values of the respective data values received by the first control shift register are arranged in a predetermined sequence that does not cause more than one row to enable the respective memory circuit of the corresponding pixel drive circuit on the row to receive a display value and store a display value as the respective data values propagate through the shift register chain.
18. 18. The method of claim 10, wherein operations performed on the plurality of word lines by the shift register data sequence are non-contiguous.

Description

Backboard and method for pulse width modulation Cross Reference to Related Applications The application claims the benefit of U.S. provisional patent application No. 63/221,536, filed on 7.14 of 2021, the entire contents of which are incorporated herein by reference. Technical Field The present invention relates to a back plate for driving a pixel driving circuit array. Background Backplanes for display devices have been manufactured using various processes for many years. The market for such devices is full of competition with other mature companies having the bid to participate. The cost of manufacturing a display device in monocrystalline silicon is relatively high. Disclosure of Invention In one embodiment, a backplane configured to drive a display includes an array of pixel drive circuits organized into a plurality of rows and a plurality of columns, each of the pixel drive circuits including a memory circuit operable to receive and store a display value, a plurality of word lines, wherein each word line is connected to the pixel drive circuits of a corresponding one of the rows, a plurality of bit lines, wherein each bit line is operable to present the display value to all of the pixel drive circuits along a corresponding one of the columns, and at least one shift register addressing component. The shift register addressing assembly includes a plurality of control shift registers, each of the control shift registers having an output operable to control a different one of the plurality of word lines, a plurality of non-control shift registers connected in series with the plurality of control shift registers to form a shift register chain, wherein a group of at least one of the plurality of non-control shift registers is logically located between sequential ones of the plurality of control shift registers, and a sequence input of a first one of the plurality of control shift registers for receiving a shift register data sequence that controls selection of the plurality of word lines in operation. In another embodiment, a method of operating a two-dimensional display of display elements includes providing a backplane that drives the two-dimensional display, the backplane comprising an array of two-dimensional pixel drive circuits organized into a plurality of rows and columns, wherein each of the pixel drive circuits comprises a corresponding memory circuit operable to receive and store display values, and in operation, to generate an output that drives a display element of the two-dimensional display from the display values stored in the corresponding memory circuit; the display device includes a plurality of rows, a plurality of columns, each of the rows having a plurality of pixel drive circuits, a plurality of word lines, each of the word lines being connected to a corresponding one of the rows, a plurality of bit lines, each of the bit lines being operable to present the display value to all of the pixel drive circuits along a corresponding one of the columns, and a shift register addressing component comprising a plurality of control shift registers, each of the control shift registers being operable to control a different one of the plurality of word lines in dependence upon a data value in the control shift register, wherein, in operation, a memory circuit of the pixel drive circuits corresponding to at least a portion of a row of the rows is selectively enabled by an action of one of the word lines to receive a display value of the display values presented by a corresponding one of the memory circuits, and a plurality of non-control shift registers, the plurality of non-control shift registers being non-operable to control any of the word lines, wherein the control shift registers and the non-control shift registers are connected in series in the shift registers, wherein a set of one or more of the non-control shift registers is logically disposed within the shift register chain between successive ones of the control shift registers such that the data value propagates through both the control shift register and the non-control shift register in response to successive cycles of a clock signal. The method further comprises inputting one data value from a shift register data sequence to a first control shift register of the plurality of control shift registers at each cycle of the clock signal, wherein the shift register data sequence is arranged such that a maximum value of one of the control shift registers operates its respective word line during any one period of the clock signal, and providing successive cycles of the clock signal to the control shift register and the non-control shift register to propagate the data value through the shift register chain. Drawings FIG. 1A presents a schematic block diagram of a backplane adapted to drive an array of pixel drive circuits in accordance with one or more embodiments. FIG. 1B presents a schematic block diagram of a backplane having a shift register