CN-117790406-B - Method for forming semiconductor structure and semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors, wherein the method for forming the semiconductor structure comprises the steps of providing a substrate, wherein the substrate comprises a plurality of active areas; forming a plurality of bit line structures on a substrate, implementing at least one circulation process to form a plurality of capacitor contact holes among the plurality of bit line structures, wherein the circulation process comprises the steps of forming a plurality of sealing layers to cover the top corners of the bit line structures, forming a slit between two adjacent sealing layers, wherein the slit is positioned in a groove, etching the substrate along the slit and the groove and exposing an active area in the substrate, removing the plurality of sealing layers, and forming a capacitor contact plug in the capacitor contact hole after implementing at least one circulation process. According to the method for forming the semiconductor structure, the top angle of the bit line structure is protected by the sealing cover layer, defects of the bit line structure are avoided, and therefore performance of the semiconductor structure is improved.

Inventors

• YUAN PAN

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260512

Application Date

20220922

Claims (13)

1. 1. The method for forming the semiconductor structure is characterized by comprising the following steps of: Providing a substrate, wherein the substrate comprises a plurality of active areas; forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures are arranged at intervals along a first direction, grooves are formed between two adjacent bit line structures, and each bit line structure extends along a second direction; performing at least one cyclic process to form a plurality of capacitive contact holes between a plurality of the bit line structures, wherein the cyclic process comprises: forming a plurality of sealing layers, wherein the sealing layers cover the top surface and part of the side surfaces of the bit line structure in a conformal manner so as to cover the top corners of the bit line structure, a slit is arranged between two adjacent sealing layers, the slit is positioned in the groove, the diameter of the slit gradually increases along the direction from the top surface to the bottom surface of the bit line structure, and the sealing layers comprise carbon and short-chain polymers of carbon; etching the substrate along the slit and the groove, and exposing an active region in the substrate; removing the plurality of the capping layers; And forming a capacitor contact plug in the capacitor contact hole after at least one cycle process is implemented.
2. 2. The method of claim 1, wherein the slit has a diameter of 1/3 to 1/2 of the trench diameter.
3. 3. The method of claim 1, wherein the capping layer covers 1/10 to 2/5 of the height of the bit line structure of the side surface of the bit line structure.
4. 4. The method of forming a semiconductor structure of claim 1, wherein a ratio between a thickness of the cap layer covering the top surface of the bit line structure and a thickness of the cap layer covering the side surface of the bit line structure is (1-3): 1.
5. 5. A method of forming a semiconductor structure according to any one of claims 1 to 3, wherein a deposition pressure for forming the capping layer in a single cycle process is 3mtorr or more and 40mtorr or less, and a height of the capping layer covering the side surface of the bit line structure is inversely proportional to a deposition pressure for forming the capping layer in the single cycle process.
6. 6. The method of claim 5, wherein a deposition time for forming the capping layer in a single cycle process is greater than or equal to 5s and less than or equal to 20s.
7. 7. The method of claim 5, comprising performing 4 to 10 cycles of the process to form a plurality of capacitive contact holes between a plurality of the bit line structures.
8. 8. The method of claim 7, wherein a deposition pressure for forming the capping layer is constant between a plurality of cyclic processes when the cyclic processes are performed.
9. 9. The method of claim 7, wherein a deposition pressure for forming the capping layer is gradually reduced between a plurality of the cyclic processes when the cyclic processes are performed.
10. 10. The method of forming a semiconductor structure of claim 9, wherein the 4 cycle process is repeated, wherein, In the 1 st cycle process, the deposition pressure for forming the sealing layer is 30-40mtorr; in the 2 nd cycle process, the deposition pressure for forming the sealing layer is 20-30mtorr; in the 3 rd cycle process, the deposition pressure for forming the capping layer is 10-20mtorr; in the 4 th cycle process, the deposition pressure for forming the capping layer is 3-10mtorr.
11. 11. The method of claim 1, wherein forming a plurality of bit line structures on the substrate comprises: depositing an initial conductive layer on the substrate, and etching the initial conductive layer along the first direction to form a plurality of conductive layers which are arranged at intervals along the first direction, wherein each conductive layer extends along the second direction; Forming a side wall layer on the surface of the conductive layer, wherein the groove is formed between adjacent side wall layers; And forming a protective layer on the side wall layer and the surface of the groove so as to protect the side wall layer and the substrate.
12. 12. The method of claim 11, wherein an etch selectivity of the capping layer and the protective layer is greater than 10.
13. 13. A semiconductor structure prepared by the method of forming a semiconductor structure as claimed in any one of claims 1 to 12.

Description

Method for forming semiconductor structure and semiconductor structure Technical Field The disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor structure and the semiconductor structure. Background As semiconductor devices have become more highly integrated, these unit devices have to be densely formed within a limited unit area, the depth of the contact hole increases and the width of the contact hole decreases due to large-scale integration. In each technical node of the semiconductor integrated circuit, the contact hole technology has a challenging difficulty, for example, when the semiconductor layer is etched in a narrow area to form a contact hole, especially when the contact hole is formed at the bottom of a trench with a high depth-to-width ratio, a certain influence is generated on the top ends of the semiconductor device structures positioned at two sides of the trench in the etching process, so that the top ends of the semiconductor device structures are worn, defects are easily caused to the devices, and further, the performance of the semiconductor devices is reduced and the yield of the semiconductor devices is obviously reduced. Disclosure of Invention The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims. The disclosure provides a method for forming a semiconductor structure and the semiconductor structure. A first aspect of the present disclosure provides a method for forming a semiconductor structure, the method for forming a semiconductor structure including: Providing a substrate, wherein the substrate comprises a plurality of active areas; forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures are arranged at intervals along a first direction, grooves are formed between two adjacent bit line structures, and each bit line structure extends along a second direction; performing at least one cyclic process to form a plurality of capacitive contact holes between a plurality of the bit line structures, wherein the cyclic process comprises: forming a plurality of cover layers, wherein the cover layers cover the top surface and part of side surfaces of the bit line structure in a conformal manner so as to cover the top corners of the bit line structure, and slits are arranged between two adjacent cover layers and are positioned in the grooves; etching the substrate along the slit and the groove, and exposing an active region in the substrate; removing the plurality of the capping layers; And forming a capacitor contact plug in the capacitor contact hole after at least one cycle process is implemented. Wherein the slit has a gradually increasing diameter in a direction along the top surface to the bottom surface of the bit line structure. Wherein the diameter of the slit accounts for 1/3 to 1/2 of the diameter of the groove. Wherein the height of the side surface of the capping layer covering the bit line structure is 1/10 to 2/5 of the height of the bit line structure. Wherein the ratio between the thickness of the capping layer covering the top surface of the bit line structure and the thickness of the capping layer covering the side surface of the bit line structure is (1-3): 1. Wherein a deposition pressure for forming the capping layer in a single cycle process is 3mtorr or more and 40mtorr or less, and a height of the capping layer covering the side surface of the bit line structure is inversely proportional to a deposition pressure for forming the capping layer in the single cycle process. Wherein the deposition time for forming the capping layer in a single cycle process is 5s or more and 20s or less. The forming method comprises the steps of implementing 4 to 10 cycle processes to form a plurality of capacitance contact holes among a plurality of bit line structures. Wherein, when a plurality of cyclic processes are implemented, the deposition pressure for forming the capping layer is constant between the plurality of cyclic processes. Wherein, when a plurality of cyclic processes are implemented, the deposition pressure for forming the capping layer gradually decreases between the cyclic processes. Wherein the 4 cycle process is repeated, wherein, In the 1 st cycle process, the deposition pressure for forming the sealing layer is 30-40mtorr; in the 2 nd cycle process, the deposition pressure for forming the sealing layer is 20-30mtorr; in the 3 rd cycle process, the deposition pressure for forming the capping layer is 10-20mtorr; in the 4 th cycle process, the deposition pressure for forming the capping layer is 3-10mtorr. Wherein the capping layer comprises carbon and a short chain polymer of carbon. The method for forming the plurality of bit line structures on the substrate comprises the following steps: depositing an initial conductive layer on the substra