CN-117794234-B - Semiconductor structure and forming method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. The semiconductor structure comprises a substrate, a fuse assembly and a fuse component, wherein the substrate comprises a first doped region, the fuse assembly comprises a contact plug and a fuse structure, the contact plug comprises a first end part electrically connected with the first doped region and a second end part extending out of the substrate along a first direction, the fuse structure is located above the second end part along the first direction, the fuse structure comprises a fuse electrode and a fuse medium layer located between the fuse electrode and the contact plug, and the first direction is perpendicular to the top surface of the substrate. The present disclosure improves the electrical performance of semiconductor structures and facilitates further miniaturization of semiconductor structure dimensions.

Inventors

• JIANG LIWEI

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260512

Application Date

20220921

Claims (16)

1. 1. A semiconductor structure, characterized in that, Comprising the following steps: a substrate including a first doped region therein; A fuse assembly including a contact plug and a fuse structure, the contact plug including a first end electrically connected to the first doped region and a second end extending out of the substrate in a first direction, the fuse structure being located above the second end in the first direction, and the fuse structure including a fuse electrode and a fuse dielectric layer located between the fuse electrode and the contact plug, the first direction being perpendicular to a top surface of the substrate; the substrate also comprises a channel region; the semiconductor structure further includes a transistor gate located on the channel region; in the first direction, a bottom surface of the fuse structure is located above a top surface of the transistor gate.
2. 2. The semiconductor structure of claim 1, wherein, The substrate also comprises a second doped region which is positioned on one side of the channel region away from the first doped region along a second direction, and the second direction is parallel to the top surface of the substrate; the semiconductor structure further includes: And the bit line is electrically connected with the second doped region, the material of the contact plug is the same as that of the bit line, and the contact plug and the bit line are arranged in the same layer.
3. 3. The semiconductor structure of claim 1, wherein, The contact plug extends along the first direction, and the first end of the contact plug extends into the first doped region, or The contact plug extends along the first direction, and the first end of the contact plug is located on the top surface of the first doped region.
4. 4. The semiconductor structure of claim 1, wherein, The fuse structure extends in the first direction, and the fuse structure includes a bottom end connected with the contact plug, and a top end of the fuse structure opposite to the bottom end of the fuse structure in the first direction; the width of the bottom end of the fuse structure along the second direction is smaller than the width of the top end of the fuse structure along the second direction, and the second direction is parallel to the top surface of the substrate.
5. 5. The semiconductor structure of claim 2, wherein, The fuse assembly further comprises a first conductive interconnection layer positioned on the second end portion of the contact plug, wherein one end of the first conductive interconnection layer is electrically connected with the contact plug, and the other end of the first conductive interconnection layer is connected with the fuse structure.
6. 6. The semiconductor structure of claim 5, wherein, The first conductive interconnect layer extends along the second direction; the fuse structure is located at an end of the first conductive interconnect layer remote from the transistor gate in the second direction.
7. 7. The semiconductor structure of claim 5, wherein, The first conductive interconnection layer comprises a first part and a second part which are distributed oppositely along a second direction; the first portion is located on the second end of the contact plug, the second portion extends out of the contact plug in the second direction, and the fuse structure is located on the second portion.
8. 8. The semiconductor structure of claim 7, wherein, The fuse structure includes: a body portion extending along the first direction and at least partially overlying a top surface of the second portion; And the extension part is connected with the main body part and extends out of the main body part along the first direction, and the extension part at least covers the side wall of the second part.
9. 9. The semiconductor structure of claim 7, wherein, Further comprises: A peripheral circuit for receiving an external control signal; And the second conductive interconnection layer is positioned on the top surface of the bit line, one end of the second conductive interconnection layer is electrically connected with the bit line, the other end of the second conductive interconnection layer is electrically connected with the peripheral circuit, and the second conductive interconnection layer and the first conductive interconnection layer are arranged in the same layer.
10. 10. The semiconductor structure of claim 5, wherein, The projection of the first conductive interconnection layer on the top surface of the substrate is completely overlapped with the projection of the contact plug on the top surface of the substrate, and the projection of the fuse structure on the top surface of the substrate is completely overlapped with the projection of the first conductive interconnection layer on the top surface of the substrate; The first conductive interconnect layer extends along the first direction, and a bottom surface of the first conductive interconnect layer is in contact electrical connection with the second end of the contact plug, and a top surface of the first conductive interconnect layer is in contact connection with the fuse structure.
11. 11. The semiconductor structure of claim 5, wherein, The fuse structure is provided with a groove; the first conductive interconnect layer extends along the first direction and is embedded within the recess.
12. 12. The semiconductor structure of claim 1, wherein, The fuse structure extends along the first direction, and the fuse structure is embedded inside the second end of the contact plug along the first direction.
13. 13. A method for forming a semiconductor structure is characterized in that, The method comprises the following steps: forming a substrate, wherein the substrate comprises a first doped region; Forming a fuse assembly on the substrate, wherein the fuse assembly comprises a contact plug and a fuse structure, the contact plug comprises a first end part electrically connected with the first doping region and a second end part extending out of the substrate along a first direction, the fuse structure is positioned above the second end part along the first direction, and comprises a fuse electrode and a fuse medium layer positioned between the fuse electrode and the contact plug, and the first direction is perpendicular to the top surface of the substrate; the substrate also comprises a channel region; the semiconductor structure further includes a transistor gate located on the channel region; in the first direction, a bottom surface of the fuse structure is located above a top surface of the transistor gate.
14. 14. The method of forming a semiconductor structure of claim 13, wherein, The substrate also comprises a channel region and a second doped region which is positioned on one side of the channel region away from the first doped region along a second direction, and the second direction is parallel to the top surface of the substrate; the step of forming a fuse assembly on the substrate includes: Forming the contact plug extending in the first direction over the first doped region while forming a bit line extending in the first direction over the second doped region; and forming the fuse structure above the contact plug.
15. 15. The method of forming a semiconductor structure of claim 14, wherein, The specific steps of forming the fuse structure above the contact plug include: Forming a first conductive interconnect layer on the second end of the contact plug, the first conductive interconnect layer being electrically connected to the second end; the fuse structure is formed on the first conductive interconnect layer.
16. 16. The method of forming a semiconductor structure of claim 15, wherein, The first conductive interconnection layer comprises a first part and a second part which are distributed oppositely along a second direction, the first part is positioned on the second end part of the contact plug, the second part extends out of the contact plug along the second direction, and the second direction is parallel to the top surface of the substrate; the specific steps of forming the fuse structure on the first conductive interconnection layer include: the fuse structure is formed on the second portion and covers at least the top surface and the sidewalls of the second portion.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic devices such as computers, and is composed of a plurality of memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected with a word line, the source is electrically connected with a bit line, and the drain is electrically connected with a capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that data information stored in the capacitor can be read or written into the capacitor through the bit line. As one-time programmable structure, a Fuse (Fuse) structure may be implemented using a capacitor. However, the capacitor of the fuse structure in the dynamic random access memory is formed synchronously with the gate in the transistor, and the structure is similar to the gate in the transistor, which not only increases the manufacturing complexity of the fuse structure, but also occupies a larger area in the memory cell, which is not beneficial to further miniaturization of the size of the semiconductor structure. In addition, because the breakdown position of the fuse structure is positioned in the substrate, the breakdown current of the fuse structure is smaller, and misjudgment is easy to occur, so that the electrical performance of the semiconductor structure is reduced. Therefore, how to further reduce the size of the semiconductor structure while improving the electrical performance of the semiconductor structure is a technical problem to be solved currently. Disclosure of Invention Some embodiments of the present disclosure provide a semiconductor structure and a method of forming the same for further reducing the size of the semiconductor structure while improving the electrical performance of the semiconductor structure. According to some embodiments, the present disclosure provides a semiconductor structure comprising: a substrate including a first doped region therein; And the fuse assembly comprises a contact plug and a fuse structure, the contact plug comprises a first end part electrically connected with the first doping region and a second end part extending out of the substrate along a first direction, the fuse structure is positioned above the second end part along the first direction, and comprises a fuse electrode and a fuse medium layer positioned between the fuse electrode and the contact plug, and the first direction is perpendicular to the top surface of the substrate. In some embodiments, the substrate further comprises a channel region and a second doped region located on one side of the channel region away from the first doped region along a second direction, wherein the second direction is parallel to the top surface of the substrate, and the semiconductor structure further comprises: And the bit line is electrically connected with the second doped region, the material of the contact plug is the same as that of the bit line, and the contact plug and the bit line are arranged in the same layer. In some embodiments, the contact plug extends in the first direction and the first end of the contact plug extends into the first doped region, or The contact plug extends along the first direction, and the first end of the contact plug is located on the top surface of the first doped region. In some embodiments, the fuse structure extends along the first direction, the fuse structure including a bottom end along a connection with the contact plug, and a top end of the fuse structure opposite the bottom end of the fuse structure along the first direction; the width of the bottom end of the fuse structure along the second direction is smaller than the width of the top end of the fuse structure along the second direction, and the second direction is parallel to the top surface of the substrate. In some embodiments, the fuse assembly further comprises: And a first conductive interconnection layer positioned on the second end part of the contact plug, wherein one end of the first conductive interconnection layer is electrically connected with the contact plug, and the other end of the first conductive interconnection layer is connected with the fuse structure. In some embodiments, the first conductive interconnect layer extends along the second direction, the semiconductor structure further comprising: a transistor gate located on the channel region; the fuse structure is located at an end of the first conductive interconnect layer remote from the transistor gate in the second direction. In some embodiments, a bottom surface of the fuse structure is located above a top surface of the transistor gate in the first direction