CN-117794235-B - Semiconductor structure, manufacturing method thereof and memory

Abstract

The embodiment of the disclosure discloses a semiconductor structure, a manufacturing method thereof and a memory, wherein the method comprises the steps of providing a stacked structure formed by alternately stacking semiconductor layers and sacrificial layers; the stacked structure comprises a first stacked region, a second stacked region connected to the first ends of the first stacked regions, insulating materials filled between the first stacked regions, a sacrificial layer for etching the second stacked region and part of the first stacked region along a first direction to form a first multi-layer gap, a semiconductor layer of the second stacked region used for forming a plurality of stacked bit line structures, a part for filling the first multi-layer gap and located in the first stacked region to form a first isolation layer, an opening perpendicular to the surface direction of the stacked structure formed in the insulating materials adjacent to the first stacked region, the first isolation layer is etched from the opening to remove at least part of the first isolation layer, a word line structure extending perpendicular to the surface direction of the stacked structure is formed at the opening, and a plurality of stacked storage structures are formed in each first stacked region.

Inventors

• ZHAO WENLI

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20220921

Claims (16)

1. 1. A method of fabricating a semiconductor structure, the method comprising: Providing a stacked structure formed by alternately stacking semiconductor layers and sacrificial layers, wherein the stacked structure comprises a plurality of first stacked regions extending along a first direction and second stacked regions connected to first ends of the first stacked regions and extending along a second direction, and insulating materials are filled between the first stacked regions; Etching the second stacking region and part of the sacrificial layer of the first stacking region along the first direction to form a first multi-layer gap; filling the part of the first multilayer gap located in the first stacking region to form a first isolation layer; forming openings in the insulating material adjacent to the first stack region perpendicular to the surface of the stack structure; Etching the first isolation layer from the opening to remove at least part of the first isolation layer; Forming a word line structure extending in a direction perpendicular to the surface of the stacked structure at the opening; And forming a plurality of stacked storage structures in the first stacking area.
2. 2. The method of claim 1, wherein an etch selectivity of the sacrificial layer material used for the sacrificial layer to the semiconductor material used for the semiconductor layer is greater than or equal to a first predetermined value.
3. 3. The method of claim 2 wherein the sacrificial layer material is silicon SiGe and the semiconductor material is silicon Si.
4. 4. The method of claim 1, wherein said filling the portion of the first multi-layer void in the first stack region forms a first isolation layer, comprising: And sequentially filling a first isolation material, a second isolation material and the first isolation material into the first multi-layer gap along the first direction to form the first isolation layer, wherein the length of the first isolation layer along the first direction is greater than or equal to the length of the first multi-layer gap in the first stacking region.
5. 5. The method of claim 4, wherein an etch selectivity of the second isolation material to the first isolation material is greater than or equal to a second predetermined value.
6. 6. The method of claim 4, wherein sequentially filling the first multi-layer void with a first spacer material, a second spacer material, and the first spacer material to form the first spacer layer comprises: filling a first isolation material into the first multilayer void; Etching the first isolation material, and reserving a part of the first isolation material located in the first stacking region; filling a second isolation material into the first multilayer void; Etching the second isolation material and reserving a part of the second isolation material located in the first stacking region, wherein the reserved second isolation material has a length of a preset grid length along the first direction; filling the first multi-layer void with the first isolation material again; the first isolation material is etched and the first isolation material is left in a portion of the first stack region and outside the second isolation material.
7. 7. The method of claim 6, wherein the etching the first isolation layer from the opening to remove at least a portion of the first isolation layer comprises: and etching the first isolation layer from the opening to remove the second isolation material in the first isolation layer.
8. 8. The method of claim 1, wherein forming a word line structure extending in a direction perpendicular to the surface of the stacked structure at the opening comprises: forming a gate oxide layer on the surface of each semiconductor layer in the opening; covering a first conductive material on the surface of the gate oxide layer to serve as a gate conductive layer; And filling a second conductive material in the opening covered with the grid conductive layer to form the word line structure.
9. 9. The method of claim 1, wherein providing a stacked structure of alternating semiconductor layers and sacrificial layers comprises: Providing a substrate; alternately stacking semiconductor materials and sacrificial layer materials on the substrate in sequence; Etching the stacked semiconductor material and sacrificial layer material along the first direction to form a plurality of first stacking regions extending along the first direction and a second stacking region connected to first ends of the plurality of first stacking regions and extending along the second direction, wherein the regions outside the stacking structure are grooves formed by etching; and filling the insulating material in the groove formed after etching.
10. 10. The method according to claim 9, wherein the method further comprises: etching the insulating material at a second end of the first stack region remote from the second stack region to form a trench between adjacent ones of the first stack regions; filling isolation materials in the grooves; removing the insulating material on one side of the second end away from the first end, and etching part of the sacrificial layer in the first stacking region from the second end along the first direction to form a second multi-layer gap; And filling the isolation material at the second end of the first stacking region where part of the sacrificial layer is etched away to form a support structure.
11. 11. The method of claim 10, wherein forming a stacked plurality of storage structures in the first stack region comprises: Removing the insulating material between the first stack regions; removing the sacrificial layer in the first stacking region to suspend each layer of the semiconductor layer; Performing metal silicidation on the surface of the semiconductor layer; covering a first metal material on the surface of the semiconductor layer after metal silicidation treatment to form a lower electrode of the capacitor structure; covering a dielectric layer on the surface of the lower electrode; Covering a third metal material on the surface of the dielectric layer to form an upper electrode of the capacitor structure; And filling polysilicon material in the gaps between the adjacent semiconductor layers with the upper electrodes and the grooves between the first stacking regions.
12. 12. The method of claim 11, wherein after forming the stacked plurality of capacitive structures, the method further comprises: Removing isolation materials at the second end of the first stacking region, and simultaneously removing at least part of the first isolation layer at one side of the capacitor structure, which is close to the first end, to form grooves at two ends of the capacitor structure; and filling an insulating material in the groove.
13. 13. The method of claim 1, wherein after forming the first isolation layer, the method further comprises: performing metal silicide treatment on the semiconductor layer which is not covered by the first isolation layer in the second stacking region along a second direction; covering the surface of the semiconductor layer with a second metal material; Etching the second metal materials at the joint of the semiconductor layers along a third direction to separate the second metal materials covered by the semiconductor layers, wherein the third direction is perpendicular to the first direction and the second direction; And filling insulating materials between the semiconductor layers covered with the second metal material and at one side of the second stacking region far away from the first stacking region, wherein the semiconductor layers covered with the second metal material are of the bit line structure.
14. 14. The method of claim 13, wherein the method further comprises: Processing the bit line structure to form a step structure with the length decreasing from bottom to top; And forming a bit line leading-out structure on each layer of the step structure.
15. 15. A semiconductor structure formed by the method of any of claims 1 to 14.
16. 16. A memory, comprising: a semiconductor structure formed by the method of any one of claims 1 to 14.

Description

Semiconductor structure, manufacturing method thereof and memory Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, and relates to a semiconductor structure, a manufacturing method thereof and a memory. Background A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and the main principle of operation is to use the amount of stored charge in a capacitor to represent whether a binary bit (bit) is a1 or a 0. In the development of DRAM, as the size is scaled further, bottlenecks encountered by vertical capacitor structures begin to appear. To achieve the increase in capacitance unit density, stacked capacitors are beginning to appear. The grid structure defined by adopting the mode of bidirectionally etching the source electrode and the drain electrode of the DRAM is easy to have an irregular shape, the performance and the quality of the DRAM are related to the regularity of the grid structure, and how to control the etching of the source electrode and the drain electrode in the DRAM to form the grid structure with a target shape becomes a problem to be solved urgently. Disclosure of Invention In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a memory. In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including: providing a stacked structure formed by alternately stacking semiconductor layers and sacrificial layers, wherein the stacked structure comprises a plurality of first stacked regions extending along a first direction and second stacked regions connected to first ends of the plurality of first stacked regions and extending along a second direction, and the first direction is perpendicular to the second direction; Etching the second stacking region and part of the sacrificial layer of the first stacking region along the first direction to form a first multi-layer gap; filling the part of the first multilayer gap located in the first stacking region to form a first isolation layer; forming openings in the insulating material adjacent to the first stack region perpendicular to the surface of the stack structure; Etching the first isolation layer from the opening to remove at least part of the first isolation layer; Forming a word line structure extending in a direction perpendicular to the surface of the stacked structure at the opening; And forming a plurality of stacked storage structures in the first stacking area. In some embodiments, an etch selectivity of the sacrificial layer material used for the sacrificial layer to the semiconductor material used for the semiconductor layer is greater than or equal to a first preset value. In some embodiments, the sacrificial layer material is silicon germanium SiGe and the semiconductor material is silicon Si. In some embodiments, the filling the portion of the first multi-layer void located in the first stack region forms a first isolation layer, comprising: And sequentially filling a first isolation material, a second isolation material and the first isolation material into the first multi-layer gap along the first direction to form the first isolation layer, wherein the length of the first isolation layer along the first direction is greater than or equal to the length of the first multi-layer gap in the first stacking region. In some embodiments, the etch selectivity of the second isolation material to the first isolation material is greater than or equal to a second preset value. In some embodiments, the filling the first multi-layer void with a first isolation material, a second isolation material, and the first isolation material in order forms the first isolation layer, including: filling a first isolation material into the first multilayer void; Etching the first isolation material, and reserving a part of the first isolation material located in the first stacking region; filling a second isolation material into the first multilayer void; Etching the second isolation material and reserving a part of the second isolation material located in the first stacking region, wherein the reserved second isolation material has a length of a preset grid length along the first direction; filling the first multi-layer void with the first isolation material again; the first isolation material is etched and the first isolation material is left in a portion of the first stack region and outside the second isolation material. In some embodiments, the etching the first isolation layer from the opening to remove at least a portion of the first isolation layer includes: and etching the first isolation layer from the opening to remove the second isolation material in the first isolation layer. In some embodiments, the forming a word line structure extending in a direction perpendicular to the surface of the stacked struc