CN-117794237-B - Semiconductor structure, forming method thereof and memory

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a forming method thereof and a memory, wherein the semiconductor structure comprises a substrate, a first dielectric layer, a conducting layer and a semiconductor layer, wherein the substrate comprises an active area, and a word line groove is formed in the active area; the semiconductor device comprises a word line groove, a first dielectric layer, a conductive layer, a semiconductor layer and a semiconductor layer, wherein the first dielectric layer is attached to the word line groove along with the shape, the conductive layer is positioned on the surface of the first dielectric layer and fills part of the word line groove, a preset gap is formed between one end of the conductive layer, which is far away from the bottom of the word line groove, and the first dielectric layer, and the semiconductor layer is positioned at the preset gap and the top of the conductive layer. The semiconductor structure of the present disclosure can reduce parasitic capacitance and reduce GIDL.

Inventors

• LU YONG
• CHEN XIAOPENG
• SONG XIAOJIE
• SUN CHUANG

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20220921

Claims (14)

1. 1. A semiconductor structure, comprising: a substrate comprising an active region having a word line trench therein; The first dielectric layer is attached in the word line groove along with the shape; the conducting layer is positioned on the surface of the first dielectric layer, fills part of the word line groove, and has a preset gap between one end of the conducting layer, which is far away from the bottom of the word line groove, and the first dielectric layer; the semiconductor layer is positioned on the preset gap and the top of the conductive layer; and a dimension of the first gap is smaller than that of the preset gap in a direction perpendicular to the extending direction of the word line groove.
2. 2. The semiconductor structure of claim 1, wherein a dimension of the conductive layer top is smaller than a dimension of the semiconductor layer in a direction perpendicular to the word line trench extension direction.
3. 3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: The second dielectric layer is positioned in the preset gap, and the semiconductor layer covers the conductive layer and the surface of the second dielectric layer.
4. 4. The semiconductor structure of claim 3, wherein a dielectric constant of the second dielectric layer is less than a dielectric constant of the first dielectric layer.
5. 5. The semiconductor structure of claim 3, wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer surrounding sidewalls and a bottom surface of the second semiconductor layer, and the second semiconductor layer having a doping concentration greater than the first semiconductor layer.
6. 6. A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises an active area, and a word line groove is formed in the active area; Forming a first dielectric layer attached along with the shape in the word line groove; Forming a conductive layer on the surface of the first dielectric layer, wherein the conductive layer fills part of the word line groove, and a preset gap is formed between one end of the conductive layer, which is far away from the bottom of the word line groove, and the first dielectric layer; Forming a semiconductor layer on top of the conductive layer; Wherein forming the semiconductor layer includes: Forming an insulating layer, wherein the insulating layer fills the preset gap and at least covers the side wall of the word line groove and the top of the conductive layer; Removing the insulating layer on top of the conductive layer; depositing a semiconductor material, the semiconductor material filling the remainder of the word line trench; Etching back the semiconductor material to form the semiconductor layer; and removing the residual insulating layer to expose the preset gap, and forming a first gap around the semiconductor layer.
7. 7. The forming method according to claim 6, wherein forming the conductive layer includes: forming a conductive material layer on the surface of the first dielectric layer; Etching back the conductive material layer to enable the thickness of the conductive material layer in the word line groove to be a preset thickness; And removing the material of the edge area of one end of the conductive material layer far away from the bottom of the word line groove, and forming the conductive layer by the rest conductive material layers.
8. 8. The forming method according to claim 6, characterized in that the forming method further comprises: and forming a first passivation layer on the surface, far away from the conductive layer, of the semiconductor layer, wherein the first passivation layer seals the opening of the first gap.
9. 9. The forming method according to claim 6 or 7, characterized in that the forming method further comprises: and filling a dielectric material in the preset gap before forming the semiconductor layer so as to form a second dielectric layer, wherein the semiconductor layer covers the surfaces of the conductive layer and the second dielectric layer.
10. 10. The method of forming of claim 9, wherein forming the second dielectric layer comprises: Depositing a dielectric material on the surface of a structure formed by the substrate, the first dielectric layer and the conductive layer together, wherein the dielectric material fills the preset gap; and removing the dielectric material positioned in the area outside the preset gap to form the second dielectric layer in the preset gap.
11. 11. The forming method according to claim 10, wherein forming the semiconductor layer includes: forming a conformal attached first semiconductor layer on the surface of a structure formed by the substrate, the first dielectric layer, the conductive layer and the second dielectric layer; Forming a second semiconductor layer on the surface of the first semiconductor layer, wherein the word line groove is filled with the second semiconductor layer; And carrying out back etching on the first semiconductor layer and the second semiconductor layer to form the semiconductor layer.
12. 12. The method of claim 11, wherein portions of the first dielectric layer on the wordline trench sidewalls are removed to level a top of the first dielectric layer on the wordline trench sidewalls with a top of the semiconductor layer when the first semiconductor layer and the second semiconductor layer are etched back.
13. 13. The forming method according to claim 12, characterized in that the forming method further comprises: And forming a second passivation layer on the surface, far away from the conductive layer, of the semiconductor layer, wherein the second passivation layer covers the first dielectric layer and the top of the semiconductor layer.
14. 14. A memory comprising the semiconductor structure of any of claims 1-5.

Description

Semiconductor structure, forming method thereof and memory Technical Field The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a forming method thereof and a memory. Background With the continuous development of mobile devices, mobile devices with battery power, such as mobile phones, tablet computers, wearable devices and the like, are increasingly applied to life, a memory is used as an indispensable element in the mobile devices, and great demands are put forward by people on the small size and integration of the memory. However, as the memory volume is continuously reduced, more and more word line structures are formed in a unit area, so that the pitch between the word line structures is reduced, resulting in an increasing parasitic capacitance between the word line structures. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention In view of the above, the present disclosure provides a semiconductor structure, a method for forming the same, and a memory device, which can reduce parasitic capacitance and GIDL. According to one aspect of the present disclosure, there is provided a semiconductor structure comprising: a substrate comprising an active region having a word line trench therein; The first dielectric layer is attached in the word line groove along with the shape; the conducting layer is positioned on the surface of the first dielectric layer, fills part of the word line groove, and has a preset gap between one end of the conducting layer, which is far away from the bottom of the word line groove, and the first dielectric layer; and the semiconductor layer is positioned on the preset gap and the top of the conductive layer. In one exemplary embodiment of the present disclosure, the conductive layer top has a smaller size than the semiconductor layer in a direction perpendicular to the word line trench extension direction. In an exemplary embodiment of the present disclosure, the semiconductor structure further includes: and a dimension of the first gap is smaller than that of the preset gap in a direction perpendicular to the extending direction of the word line groove. In an exemplary embodiment of the present disclosure, the semiconductor structure further includes: The second dielectric layer is positioned in the preset gap, and the semiconductor layer covers the conductive layer and the surface of the second dielectric layer. In one exemplary embodiment of the present disclosure, the second dielectric layer has a dielectric constant that is less than a dielectric constant of the first dielectric layer. In one exemplary embodiment of the present disclosure, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer surrounds sidewalls and a bottom surface of the second semiconductor layer, and a doping concentration of the second semiconductor layer is greater than that of the first semiconductor layer. According to one aspect of the present disclosure, there is provided a method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises an active area, and a word line groove is formed in the active area; Forming a first dielectric layer attached along with the shape in the word line groove; Forming a conductive layer on the surface of the first dielectric layer, wherein the conductive layer fills part of the word line groove, and a preset gap is formed between one end of the conductive layer, which is far away from the bottom of the word line groove, and the first dielectric layer; A semiconductor layer is formed on top of the conductive layer. In one exemplary embodiment of the present disclosure, forming the conductive layer includes: forming a conductive material layer on the surface of the first dielectric layer; Etching back the conductive material layer to enable the thickness of the conductive material layer in the word line groove to be a preset thickness; And removing the material of the edge area of one end of the conductive material layer far away from the bottom of the word line groove, and forming the conductive layer by the rest conductive material layers. In one exemplary embodiment of the present disclosure, forming the semiconductor layer includes: Forming an insulating layer, wherein the insulating layer fills the preset gap and at least covers the side wall of the word line groove and the top of the conductive layer; Removing the insulating layer on top of the conductive layer; depositing a semiconductor material, the semiconductor material filling the remainder of the word line trench; Etching back the semiconductor material to form the semiconductor laye