CN-117809546-B - Gate driving circuit and display panel

Abstract

The embodiment of the application provides a gate driving circuit and a display panel, wherein the gate driving circuit comprises a multi-stage cascade gate driving unit, the gate driving unit comprises a pull-up control module, an output module, a pull-down maintaining module, a first reference low-level signal input end, a second reference low-level signal input end and a pull-up node positioned in a circuit between the pull-up control module and the output module, the pull-up control module comprises a pull-up control transistor, the pull-up control transistor is electrically connected with the pull-up node and is used for pulling up the potential of the pull-up node, the output module comprises a scanning signal output transistor, the scanning signal output transistor is electrically connected with the pull-up node and is used for outputting a local scanning signal under the control of the potential of the pull-up node, and the ratio of the channel length of the pull-up control transistor to the channel length of the scanning signal output transistor is between 1:8 and 1:12.

Inventors

• HE SONG
• HE XIAOJIN
• WANG XU
• YANG ZELIN

Assignees

• TCL华星光电技术有限公司

Dates

Publication Date

20260512

Application Date

20231214

Claims (11)

1. 1. The grid driving circuit is characterized by comprising a multi-stage cascade grid driving unit, wherein the grid driving unit comprises a pull-up control module, an output module, a pull-down maintenance module, a first reference low-level signal input end, a second reference low-level signal input end and a pull-up node positioned in a circuit between the pull-up control module and the output module; The pull-up control module comprises a pull-up control transistor, wherein the pull-up control transistor is electrically connected with the pull-up node and is used for pulling up the potential of the pull-up node; The output module comprises a scanning signal output transistor, wherein the scanning signal output transistor is electrically connected with the pull-up node and is used for outputting a current stage scanning signal under the control of the potential of the pull-up node; The pull-down module is electrically connected with the pull-up node, the first reference low-level signal input end and the pull-down maintaining module, and is used for pulling down the potential of the pull-up node to the potential of the first reference low-level signal input by the first reference low-level signal input end; The pull-down maintaining module is electrically connected with the pull-up node and the second reference low-level signal input end, and is used for enabling the potential of the pull-up node to be kept at the potential of the second reference low-level signal input by the second reference low-level signal input end; The ratio of the channel length of the pull-up control transistor to the channel length of the scanning signal output transistor is between 1:8 and 1:12.
2. 2. The gate driving circuit according to claim 1, wherein a channel length of the scan signal output transistor is between 12000 micrometers and 33000 micrometers.
3. 3. The gate drive circuit of claim 1, wherein the pull-down module comprises a first pull-down transistor and a second pull-down transistor; The first electrode of the first pull-down transistor is electrically connected with the first electrode of the second pull-down transistor and the pull-up node, the second electrode of the first pull-down transistor is electrically connected with the second electrode of the second pull-down transistor and the first reference low-level signal input end, the grid electrode of the first pull-down transistor is electrically connected with the first control signal input end, the grid electrode of the second pull-down transistor is electrically connected with the second control signal end, and the first pull-down transistor and the second pull-down transistor are used for pulling down the potential of the pull-up node; The sum of the channel length of the first pull-down transistor and the channel length of the second pull-down transistor is greater than or equal to the channel length of the pull-up control transistor.
4. 4. The gate driving circuit of claim 3, wherein the pull-down module comprises a third pull-down transistor, a first electrode of the third pull-down transistor being electrically connected to the first electrode of the second pull-down transistor and the pull-up node, a second electrode of the third pull-down transistor being electrically connected to the second electrode of the second pull-down transistor and the first reference low-level signal input terminal; The sum of the channel length of the third pull-down transistor and the channel length of the first pull-down transistor and the channel length of the second pull-down transistor is greater than or equal to the channel length of the pull-up control transistor.
5. 5. The gate drive circuit of claim 3 or 4, wherein a ratio of a sum of channel lengths of the first pull-down transistor and the second pull-down transistor to a channel length of the pull-up control transistor is between 1:1 and 1.4:1.
6. 6. The gate drive circuit of claim 4, wherein a ratio of a sum of channel lengths of the first pull-down transistor and the third pull-down transistor to a channel length of the pull-up control transistor is between 1:1 and 1.4:1.
7. 7. The gate driving circuit of claim 1, wherein the pull-down maintaining module comprises a first pull-down maintaining transistor, a second pull-down maintaining transistor, a third pull-down maintaining transistor, and a fourth pull-down maintaining transistor; the grid electrode and the first electrode of the first pull-down maintaining transistor are electrically connected with the first clock signal input end, and the second electrode of the first pull-down maintaining transistor is electrically connected with the first electrode of the second pull-down maintaining transistor; The grid electrode of the second pull-down maintaining transistor is electrically connected with the pull-up node, and the second electrode of the second pull-down maintaining transistor is electrically connected with the second reference low-level signal input end; A first electrode of the third pull-down maintaining transistor is electrically connected with the first clock signal input end, a grid electrode of the third pull-down maintaining transistor is electrically connected with a second electrode of the first pull-down maintaining transistor, and a second electrode of the third pull-down maintaining transistor is electrically connected with a first electrode of the fourth pull-down maintaining transistor; A gate of the fourth pull-down maintaining transistor is electrically connected with the pull-up node, a second electrode of the fourth pull-down maintaining transistor is electrically connected with the second reference low level signal input end, and the first pull-down maintaining transistor, the second pull-down maintaining transistor, the third pull-down maintaining transistor and the fourth pull-down maintaining transistor are used for keeping a potential of the pull-up node at a low potential; The ratio of the channel length of the first pull-down maintaining transistor to the channel length of the second pull-down maintaining transistor is between 1:4 and 1:8.
8. 8. The gate driving circuit according to claim 7, wherein a ratio of a current value flowing through the second electrode of the fourth pull-down maintaining transistor to a current value flowing through the second electrode of the third pull-down maintaining transistor is equal to M times a ratio of a difference between a voltage value applied to the gate of the fourth pull-down maintaining transistor and a voltage value applied to the second electrode of the fourth pull-down maintaining transistor and a difference between a voltage value applied to the gate of the third pull-down maintaining transistor and a voltage value applied to the second electrode of the third pull-down maintaining transistor, M being a positive integer greater than 4.
9. 9. The gate driving circuit of claim 7, wherein the pull-down maintaining module comprises a fifth pull-down maintaining transistor and a sixth pull-down maintaining transistor; The grid electrode of the fifth pull-down maintaining transistor is electrically connected with the pull-up node of the upper X-stage grid driving unit, the first electrode of the fifth pull-down maintaining transistor is electrically connected with the second electrode of the first pull-down maintaining transistor, the second electrode of the fifth pull-down maintaining transistor is electrically connected with the second reference low-level signal input end, and X is a positive integer greater than or equal to 1; The grid electrode of the sixth pull-down maintaining transistor is electrically connected with the pull-up node of the upper X-stage grid driving unit, the first electrode of the sixth pull-down maintaining transistor is electrically connected with the second electrode of the third pull-down maintaining transistor, and the second electrode of the sixth pull-down maintaining transistor is electrically connected with the second reference low-level signal input end; the channel length of the first pull-down maintaining transistor is equal to the channel length of the fifth pull-down maintaining transistor, and the channel length of the second pull-down maintaining transistor is equal to the channel length of the sixth pull-down maintaining transistor.
10. 10. The gate drive circuit of claim 7, wherein a voltage value of a gate of the third pull-down holding transistor and a second electrode of the third pull-down holding transistor is between 24.52 volts and 26.84 volts during an on period of the first pull-down holding transistor and the third pull-down holding transistor.
11. 11. A display panel comprising a plurality of pixel cells and a gate drive circuit according to any one of claims 1 to 10, the gate drive circuit being electrically connected to a plurality of the pixel cells.

Description

Gate driving circuit and display panel Technical Field The application relates to the technical field of display, in particular to a gate driving circuit and a display panel. Background The Gate-driver On Array (GOA) technology is a technology for manufacturing a Gate driving circuit On a thin film transistor Array substrate by using a process of the thin film transistor Array (Array) to realize a progressive scanning driving mode. The gate driving circuit includes a multistage cascade of gate driving units. The transistors in the existing gate driving units are easily affected by parasitic capacitance and the like, thereby affecting the potential of the pull-up node, resulting in poor stability of the existing gate driving circuits. Disclosure of Invention An embodiment of the application is directed to a gate driving circuit and a display panel, in which the stability of the gate driving circuit is high. In one aspect, an embodiment of the application provides a gate driving circuit, which comprises a multi-stage cascade gate driving unit, wherein the gate driving unit comprises a pull-up control module, an output module, a pull-down maintaining module, a first reference low-level signal input end, a second reference low-level signal input end and a pull-up node positioned in a line between the pull-up control module and the output module, the pull-up control module comprises a pull-up control transistor, the pull-up control transistor is electrically connected with the pull-up node, the pull-up control transistor is used for pulling up the potential of the pull-up node, the output module comprises a scanning signal output transistor, the scanning signal output transistor is electrically connected with the pull-up node, the scanning signal output transistor is used for outputting a current level scanning signal under the control of the potential of the pull-up node, the pull-down module is electrically connected with the pull-up node, the first reference low-level signal input end and the pull-down maintaining module, the pull-down module is used for electrically connecting the pull-down node to the first reference low-level signal input end and the pull-level signal input end, the first reference low-level signal input end and the pull-level signal input end is electrically connected with the pull-down maintaining module, the second reference low-level signal input end is connected with the second reference signal input end, and the second reference signal input end is kept at a high-level ratio between the first input end and the second input end and the potential and the second input end is kept at the potential and the potential 1. Optionally, in some embodiments of the present application, a channel length of the scan signal output transistor is between 12000 micrometers and 33000 micrometers. Optionally, in some embodiments of the present application, the pull-down module includes a first pull-down transistor and a second pull-down transistor, a first electrode of the first pull-down transistor is electrically connected to a first electrode of the second pull-down transistor and the pull-up node, a second electrode of the first pull-down transistor is electrically connected to a second electrode of the second pull-down transistor and a first reference low level signal input terminal, a gate of the first pull-down transistor is electrically connected to a first control signal input terminal, a gate of the second pull-down transistor is electrically connected to a second control signal terminal, the first pull-down transistor and the second pull-down transistor are used for pulling down a potential of the pull-up node, and a sum of a channel length of the first pull-down transistor and a channel length of the second pull-down transistor is greater than or equal to a channel length of the pull-up control transistor. Optionally, in some embodiments of the present application, the pull-down module includes a third pull-down transistor, a first electrode of the third pull-down transistor is electrically connected to the first electrode of the second pull-down transistor and the pull-up node, a second electrode of the third pull-down transistor is electrically connected to the second electrode of the second pull-down transistor and the first reference low level signal input terminal, and a sum of a channel length of the third pull-down transistor and a channel length of the first pull-down transistor and a channel length of the second pull-down transistor is greater than or equal to a channel length of the pull-up control transistor. Optionally, in some embodiments of the present application, a ratio of a sum of channel lengths of the first pull-down transistor and the second pull-down transistor to a channel length of the pull-up control transistor is between 1:1 and 1.4:1, or a ratio of a sum of channel lengths of the first pull-down transistor and the third pull-down transistor to a channel length of th