CN-117831486-B - Frame memory scheduling system based on variable refresh rate

CN117831486BCN 117831486 BCN117831486 BCN 117831486BCN-117831486-B

Abstract

The invention belongs to the technical field of head-up display character video image processing, in particular to a frame memory scheduling system based on variable refresh rate, which comprises an input video time sequence detection unit, an output video time sequence generation unit, a read-out frame scheduling unit, a video buffer memory unit, a write-in frame buffer memory scheduling unit and a storage read-write control unit, wherein the write-in frame buffer memory scheduling unit adopts a three-frame buffer memory round-robin writing algorithm which writes video into the storage read-write control unit, the generated current written video frame buffer number information is input into a read frame scheduling unit, and the read frame scheduling unit calculates the frame buffer number to be read currently according to the received time sequence information of the output video and the current written video frame buffer number information.

Inventors

WANG JIAHUI
GUO ZHENCHAO
WANG ZEBIN
ZHAO YUFEI
SHEN JINGJING
NIU PANQING

Assignees

中国航空工业集团公司洛阳电光设备研究所

Dates

Publication Date: 20260505
Application Date: 20231109

Claims (4)

1. A frame memory scheduling system based on variable refresh rate is characterized by comprising an input video time sequence detection unit, an output video time sequence generation unit, a read-out frame scheduling unit, a video buffer unit, a write-in frame buffer scheduling unit and a storage read-write control unit, The video buffer unit is connected with an input video signal, performs first-level buffer on the input video signal, and then inputs the video signal into the writing frame buffer scheduling unit; The storage read-write control unit is respectively communicated with the write-in frame buffer scheduling unit and the read-out frame scheduling unit through logic control signals, a three-frame buffer round-robin writing algorithm is adopted by the scheduling algorithm of the write-in frame buffer scheduling unit, three frame buffer areas are virtually instantiated in the storage read-write control unit and are numbered 1,2 and 3, the three-frame buffer round-robin writing algorithm circularly writes videos into the storage read-write control unit according to the sequence of 1-2-3-1, and meanwhile, the generated current written video frame buffer number information is input into the read-out frame scheduling unit; the output video time sequence generating unit receives the video signal processed by the input video time sequence detecting unit, then generates time sequence information of the corresponding output video, and inputs the time sequence information into the read-out frame scheduling unit; the read-out frame scheduling unit calculates a frame buffer number to be read currently according to the received time sequence information of the output video and the current written video frame buffer number information, then proposes corresponding video information from the storage read-write control unit, and then outputs the video information to the outside of the system through the frame output scheduling unit; the input video time sequence detection unit is connected with the input video signal and is used for acquiring whether the input video finishes writing one frame or not in real time.
2. The frame memory scheduling system based on the variable refresh rate of claim 1, wherein the output end of the writing frame buffer scheduling unit is connected with the storage read-write control unit through a bus, and is used for realizing the scheduling of writing the input video into the frame buffer.
3. The frame memory scheduling system realized based on the variable refresh rate according to claim 2, wherein the input end of the read frame scheduling unit is connected with the state output ends of the write frame buffer scheduling unit and the output video time sequence generating unit through an instruction signal line, and is used for acquiring information required by read frame scheduling.
4. The frame memory scheduling system realized based on the variable refresh rate according to claim 3, wherein an input end of said read-out frame scheduling unit is connected to the memory read-write control unit via a bus, for realizing frame buffer data read control of a designated number.

Description

Frame memory scheduling system based on variable refresh rate Technical Field The invention belongs to the technical field of character video image processing of head-up displays, and particularly relates to a frame memory scheduling system realized based on a variable refresh rate. Background The old head-up display adopts a CRT image source, and along with the technical development, CRT is gradually replaced by a digital image source so as to face production stoppage, meanwhile, in order to achieve better display effect, the CRT head-up display is converted into a digital head-up display, after the CRT is converted into digital, the sampling and digital processing links in the digital scheme are inevitably increased due to the change of a scanning mode, analog deflection and highlighting signals in the original CRT scheme are directly driven to scan and display after being amplified by a response analog circuit, and the deflection scanning mode in the digital scheme is converted into a line scanning mode of the digital image source, so that new delay display influence is caused on video information conversion, and the conversion of the scanning modes, the processing and the display of the digital signals can obviously increase the delay of the display, so that the use of the head-up display is influenced, and the processing cannot be carried out through the existing technology. Therefore, a frame memory scheduling system based on a variable refresh rate is needed to realize a variable refresh rate technical scheme to meet the requirement of controlling the output delay within one frame (20 ms) aiming at the problem that the digital time sequences of the prior input signal and the output signal are not matched. Disclosure of Invention In view of this, the invention provides a frame memory scheduling system based on variable refresh rate, which dynamically matches and binds the output digital time sequence with the input analog time sequence by dynamically matching the output refresh rate, thereby greatly reducing video output delay and having high value. In order to achieve the technical purpose, the invention adopts the following specific technical scheme: The frame memory scheduling system based on the variable refresh rate comprises an input video time sequence detection unit, an output video time sequence generation unit, a read-out frame scheduling unit, a video buffer unit, a write-in frame buffer scheduling unit and a storage read-write control unit, wherein the video buffer unit is connected with an input video signal, the input video signal is subjected to first-level buffer storage and then is input into the write-in frame buffer scheduling unit, the storage read-write control unit is respectively communicated with the write-in frame buffer scheduling unit and the read-out frame scheduling unit through logic control signals, the three-frame buffer rotation write algorithm is used for virtually instantiating three frame buffer areas in the storage read-write control unit and numbering as 1,2 and 3, the three-frame buffer rotation write algorithm circularly writes video into the storage read-write control unit according to the sequence of 1-2-3-1, meanwhile, the generated current write video frame buffer numbering information is input into the read-out frame buffer scheduling unit, the output video time sequence generation unit receives the video signal processed by the input video time sequence detection unit and then generates the corresponding video signal, the three-frame buffer rotation write algorithm is read-out frame buffer storage scheduling unit, the current frame number information is read-out of the video buffer storage control unit, and the current frame number information is required to be read out from the read-out frame buffer scheduling unit, and the current frame number information is read out from the video time sequence control unit, and the current frame number is required to be read out from the video frame buffer storage unit. Furthermore, the output end of the writing frame buffer memory scheduling unit is connected with the storage read-write control unit through a bus and is used for realizing the scheduling of the writing frame buffer memory of the input video. Further, the input video timing sequence detecting unit is connected with the input video signal and is used for acquiring whether the input video finishes writing one frame or not in real time. Further, the input end of the read-out frame scheduling unit is connected with the state output ends of the write-in frame buffer scheduling unit and the output video time sequence generating unit through an instruction signal line, and is used for acquiring information required by read-out frame scheduling. Further, the input end of the read-out frame scheduling unit is connected with the storage read-write control unit through a bus, and is used for realizing frame buffer data read control of a designated number. By adopt