CN-117850540-B - Clock synchronization method and device for chip tester, electronic equipment and storage medium

CN117850540BCN 117850540 BCN117850540 BCN 117850540BCN-117850540-B

Abstract

The present application relates to the field of chip testing technologies, and in particular, to a clock synchronization method and apparatus for a chip tester, an electronic device, and a storage medium. The chip testing machine comprises a main backboard and a plurality of slave backboard, wherein the main backboard comprises a high-precision clock chip and a first programmable logic chip, the method comprises the steps of responding to an instruction for clock synchronization processing, configuring and sending a low-frequency detection clock signal with preset frequency, configuring a high-precision clock signal with target frequency based on the high-precision clock chip when the low-frequency detection clock signal is detected, enabling the target frequency to be higher than the preset frequency, and sending the high-precision clock signal to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip when the clock signal currently acquired by the first programmable logic chip and the second programmable logic chip is verified to meet preset state constraint conditions, so that clock synchronization of all testing boards is completed. The method can be used for realizing the precision and stability of clock synchronization processing.

Inventors

CAI GONGHUA
DONG YAMING
CHEN HUAN

Assignees

苏州华兴源创科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20240112

Claims (10)

1. The clock synchronization method of the chip tester is characterized in that the chip tester comprises a main backboard and a plurality of slave backboard, the main backboard and the slave backboard are both in communication connection with a plurality of test boards, the main backboard comprises a high-precision clock chip and a first programmable logic chip, the slave backboard comprises a second programmable logic chip, and the method comprises the following steps: Responding to an instruction for carrying out clock synchronization processing on a plurality of test boards, configuring and sending a low-frequency detection clock signal with preset frequency to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip; When the first programmable logic chip detects the low-frequency detection clock signal, configuring a high-precision clock signal with a target frequency based on the high-precision clock chip, wherein the target frequency is higher than the preset frequency; When the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are verified to meet the preset state constraint conditions, the high-precision clock signals are sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chips so as to complete clock synchronization of all the test boards.
2. The method of claim 1, wherein when the first programmable logic chip detects the low frequency detection clock signal, further comprising: transmitting a trigger signal to the second programmable logic chip based on the first programmable logic chip; And indicating the first programmable logic chip and the second programmable logic chip to synchronously time based on the trigger signal.
3. The method of claim 2, wherein the indicating the first programmable logic chip and the second programmable logic chip to synchronize timing based on the trigger signal comprises: When the timing of the first programmable logic chip reaches a first preset time length and the timing of the second programmable logic chip reaches a second preset time length, judging that the start flag bits of the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are consistent, wherein the first preset time length is the sum of the second preset time length and the period of the low-frequency detection clock signals.
4. The method of claim 3, wherein the indicating the first programmable logic chip and the second programmable logic chip based on the trigger signal further comprises, prior to synchronizing the timing: and closing the test board card and an enabling channel between the main backboard and the slave backboard which are associated with the test board card.
5. The method of claim 4, wherein after the configuring and transmitting the low frequency detection clock signal of the preset frequency to the first programmable logic chip and the second programmable logic chip based on the high precision clock chip, further comprises: setting the start flag bit and starting timing in response to the detected master back plate and the slave back plate; When the second programmable logic chip reaches the second preset duration, judging that the high-precision clock signals acquired by the first programmable logic chip and the second programmable logic chip are finished synchronously; and opening the enabling channel to send the high-precision clock signal to the opposite target test board card based on the target backboard.
6. The method of claim 2, wherein the master backplane comprises a first system clock chip and the slave backplane comprises a second system clock chip, the method further comprising, prior to responding to the instruction to clock synchronize processing the plurality of test boards: And configuring initial clocks of the corresponding back boards based on the first system clock chip and the second system clock chip so as to enable the master back board and the slave back boards to complete system clock configuration.
7. The method of claim 6, wherein the trigger signal is a synchronization start pulse signal generated by the first programmable logic chip at a rising edge of the low frequency detection clock signal with the system clock as a reference clock.
8. The utility model provides a chip tester clock synchronizer, its characterized in that, chip tester includes main backplate and a plurality of from backplate, main backplate with all communication connection from the backplate has a plurality of test boards, main backplate includes high accuracy clock chip and first programmable logic chip, from the backplate including the second programmable logic chip, the device includes: the low-frequency detection clock module is used for responding to an instruction for carrying out clock synchronization processing on a plurality of test boards, configuring and sending a low-frequency detection clock signal with preset frequency to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip; the high-precision clock configuration module is used for configuring a high-precision clock signal with a target frequency based on the high-precision clock chip when the first programmable logic chip detects the low-frequency detection clock signal, wherein the target frequency is higher than the preset frequency; And the clock synchronization module is used for sending the high-precision clock signal to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip when the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are verified to meet the preset state constraint condition, so that clock synchronization of all the test boards is completed.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
10. An electronic device comprising at least one processor and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and wherein the at least one processor implements a method of clock synchronization of a chip tester as claimed in any one of claims 1-7 by executing the instructions stored by the memory.

Description

Clock synchronization method and device for chip tester, electronic equipment and storage medium Technical Field The present application relates to the field of chip testing technologies, and in particular, to a clock synchronization method and apparatus for a chip tester, an electronic device, and a storage medium. Background A digital chip tester is a specialized device used to test and verify the performance and functionality of digital chips (e.g., integrated circuits, processors, FPGAs, etc.). It is typically composed of hardware and software, and various tests and measurements can be performed on the chip to ensure that it is functioning properly within the design specifications and expected performance range. The digital chip tester can perform functions such as electrical testing, timing testing, logic function testing, performance testing, reliability testing, and the like. Digital chip testers play an important role in chip design and production processes, and can help developers and manufacturers ensure the quality and performance of chips, and discover and solve potential problems and defects. In order to ensure the reliability of the chip, the digital chip tester generally uses pattern (time sequence chip) test to judge whether the chip functions normally, thereby realizing rapid test of large-scale mass production of the digital chip. The digital chip tester generally supports hundreds of pattern test channels, such as 512, 768, 1024 channels, etc., and the pattern digital waveform output by each channel needs to be output to the pins of the digital chip to be tested at the same time, i.e. the pattern digital chip needs to be aligned with edges so as to ensure that the timing sequence among signals output to the pins of the digital chip to be tested is correct. For this purpose, to ensure that the edges of the digital waveforms output by all pattern channels of all digital chip testers are aligned, the clocks of each digital measurement transaction are synchronized. In the related art, in order to synchronize clock signals of a plurality of digital chip testers, it is generally necessary to connect a plurality of test backplanes according to a master-slave mode between each other, and make the pattern module detect the start of a clock by using the first edge trigger of an input clock, that is, it is necessary to ensure that the first edge of a clock entering the pattern module for controlling synchronization must be completely synchronized. However, the clock synchronization method of the current digital chip tester has the following technical problems: different chip testers may have different proprietary clock chips, so that during clock switching, the pattern module has difficulty in detecting the first edge of the latest clock according to a unified standard, and clock synchronization processing is difficult. Disclosure of Invention In view of the foregoing, there is a need for a method, apparatus, electronic device, and computer-readable storage medium for clock synchronization of a chip tester that can improve the accuracy and stability of clock synchronization processing of a plurality of chip testers in a multi-chip tester system. In a first aspect, the present application provides a method for clock synchronization of a chip tester. The chip tester comprises a main backboard and a plurality of slave backboard, wherein the main backboard and the slave backboard are all in communication connection with a plurality of test boards, the main backboard comprises a high-precision clock chip and a first programmable logic chip, the slave backboard comprises a second programmable logic chip, and the method comprises the following steps: Responding to an instruction for carrying out clock synchronization processing on a plurality of test boards, configuring and sending a low-frequency detection clock signal with preset frequency to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chip; When the first programmable logic chip detects the low-frequency detection clock signal, configuring a high-precision clock signal with a target frequency based on the high-precision clock chip, wherein the target frequency is higher than the preset frequency; When the clock signals currently acquired by the first programmable logic chip and the second programmable logic chip are verified to meet the preset state constraint conditions, the high-precision clock signals are sent to the first programmable logic chip and the second programmable logic chip based on the high-precision clock chips so as to complete clock synchronization of all the test boards. In one embodiment, when the first programmable logic chip detects the low frequency detection clock signal, the method further includes: transmitting a trigger signal to the second programmable logic chip based on the first programmable logic chip; And indicating the first programmable logic chip and the s