Search

CN-117877414-B - Display panel

CN117877414BCN 117877414 BCN117877414 BCN 117877414BCN-117877414-B

Abstract

The application discloses a display panel which comprises a first display area, a second display area at least partially surrounding the first display area, a plurality of first pixel circuits and a plurality of second pixel circuits, wherein the first pixel circuits are positioned in the first display area, the second pixel circuits are positioned in the second display area, the first pixel circuits comprise a first transistor, a second transistor, a third transistor, a fourth transistor and at least two first light emitting devices, the control end of the third transistor is electrically connected with a reset signal control end, one of the source electrode or the drain electrode of the third transistor is electrically connected with a first reset signal input end, the other of the source electrode or the drain electrode of the third transistor is electrically connected with a first node, the control end of the fourth transistor is electrically connected with a reset signal control end, one of the source electrode or the drain electrode of the fourth transistor is electrically connected with a first reset signal input end, and the other of the source electrode or the drain electrode of the fourth transistor is electrically connected with a third node.

Inventors

  • LI KUI

Assignees

  • 武汉华星光电半导体显示技术有限公司

Dates

Publication Date
20260512
Application Date
20240115

Claims (9)

  1. 1. The display panel is characterized by comprising a first display area and a second display area at least partially surrounding the first display area, wherein the display panel further comprises a power supply voltage input end, a scanning signal input end, a light-emitting control signal end, a data signal input end, a reset signal control end, a first reset signal input end, a second reset signal input end, a plurality of first pixel circuits and a plurality of second pixel circuits, the first pixel circuits are positioned in the first display area, the second pixel circuits are positioned in the second display area, and the first pixel circuits comprise a first transistor, a second transistor, a third transistor, a fourth transistor and at least two first light-emitting devices; The control end of the first transistor is electrically connected with a first node, one of a source electrode or a drain electrode of the first transistor is electrically connected with a second node, the other of the source electrode or the drain electrode of the first transistor is electrically connected with a third node, and the second node is electrically connected with the power supply voltage input end; The control end of the second transistor is electrically connected with the scanning signal input end, one of a source electrode or a drain electrode of the second transistor is electrically connected with the data signal input end, and the other of the source electrode or the drain electrode of the second transistor is electrically connected with the second node; The control end of the third transistor is electrically connected with the reset signal control end, one of a source electrode or a drain electrode of the third transistor is electrically connected with the first reset signal input end, and the other of the source electrode or the drain electrode of the third transistor is electrically connected with the first node; The control end of the fourth transistor is electrically connected with the reset signal control end, one of a source electrode or a drain electrode of the fourth transistor is electrically connected with the first reset signal input end, and the other of the source electrode or the drain electrode of the fourth transistor is electrically connected with the third node; Anodes of the two first light emitting devices are electrically connected with the third node; The second pixel circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a second light emitting device, wherein the control end of the tenth transistor is electrically connected with the reset signal control end, one of a source electrode or a drain electrode of the tenth transistor is electrically connected with the first reset signal input end, the control end of the eleventh transistor is electrically connected with the reset signal control end, one of the source electrode or the drain electrode of the eleventh transistor is electrically connected with the second reset signal input end, and a voltage signal of the first reset signal input end is different from a voltage signal of the second reset signal input end; Wherein the third transistor and the tenth transistor are double-gate transistors.
  2. 2. The display panel of claim 1, wherein the first pixel circuit further comprises: and a fifth transistor having a control terminal electrically connected to the scan signal input terminal, one of a source and a drain electrically connected to the first node, and the other of the source and the drain electrically connected to the third node.
  3. 3. The display panel of claim 2, wherein the first pixel circuit further comprises: a sixth transistor, a control terminal of which is electrically connected to the emission control signal terminal, one of a source or a drain of which is electrically connected to the power supply voltage input terminal, and the other of the source or the drain of which is electrically connected to the second node; and a seventh transistor, a control terminal of the seventh transistor is electrically connected to the emission control signal terminal, one of a source and a drain of the seventh transistor is electrically connected to the third node, and the other of the source and the drain of the seventh transistor is electrically connected to the anode of the first light emitting device.
  4. 4. The display panel according to claim 2, wherein the first pixel circuit further comprises a first capacitor, one end of the first capacitor is electrically connected to the power supply voltage input terminal, and the other end of the first capacitor is electrically connected to the first node.
  5. 5. The display panel according to any one of claims 1 to 4, wherein a control terminal of the eighth transistor is electrically connected to a fourth node, one of a source or a drain of the eighth transistor is electrically connected to a fifth node, the other of the source or the drain of the eighth transistor is electrically connected to a sixth node, and the fourth node is electrically connected to the power supply voltage input terminal; A control terminal of the ninth transistor is electrically connected to the scan signal input terminal, one of a source and a drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source and the drain of the ninth transistor is electrically connected to the fifth node; the other of the source or the drain of the tenth transistor is electrically connected to the fourth node; The other of the source or the drain of the eleventh transistor is electrically connected to the sixth node; Anodes of the two second light emitting devices are electrically connected to the sixth node.
  6. 6. The display panel of claim 5, wherein the second pixel circuit further comprises: a twelfth transistor having a control terminal electrically connected to the scan signal input terminal, one of a source and a drain electrically connected to the fourth node, and the other of the source and the drain electrically connected to the sixth node.
  7. 7. The display panel of claim 6, wherein the first pixel circuit further comprises: A thirteenth transistor having a control terminal electrically connected to the emission control signal terminal, one of a source or a drain of the thirteenth transistor being electrically connected to the power supply voltage input terminal, the other of the source or the drain of the thirteenth transistor being electrically connected to the fifth node; a fourteenth transistor having a control terminal electrically connected to the emission control signal terminal, one of a source or a drain of the fourteenth transistor being electrically connected to the sixth node, and the other of the source or the drain of the fourteenth transistor being electrically connected to the anode of the second light emitting device.
  8. 8. The display panel according to claim 6, wherein the first pixel circuit further comprises a second capacitor, one end of the second capacitor is electrically connected to the power supply voltage input terminal, and the other end of the second capacitor is electrically connected to the fourth node.
  9. 9. The display panel of claim 5, wherein a voltage of the first reset signal input is greater than a voltage of the second reset signal input.

Description

Display panel Technical Field The application relates to the technical field of display panels, in particular to a display panel. Background In a display device adopting a full screen, in order to realize the functions of self-photographing and visual communication, a camera is arranged in a camera area of a display panel, and pixel circuits with the same structure are arranged in the display area and the camera area of the existing display panel, namely, each pixel circuit in the display area controls one light emitting device to work, and each pixel circuit in the camera area controls one light emitting device to work. In order to improve the transmittance of the camera area of the display panel, each pixel circuit in the camera area controls two light emitting devices to work, and as the number of the light emitting devices controlled by each pixel circuit in the camera area is increased, a stay wire of the camera area is lengthened, the area of an anode of the light emitting device is increased, the transmittance of the camera area is reduced, and therefore the photographing effect of the camera is affected. Disclosure of Invention The embodiment of the application provides a display panel, which is used for improving the transmittance of a camera area of the display panel. In a first aspect, an embodiment of the present application provides a display panel, including a first display area and a second display area at least partially surrounding the first display area, where the display panel further includes a power supply voltage input terminal, a scan signal input terminal, a light emission control signal terminal, a data signal input terminal, a reset signal control terminal, a first reset signal input terminal, a second reset signal input terminal, a plurality of first pixel circuits and a plurality of second pixel circuits, where the first pixel circuits are located in the first display area, the second pixel circuits are located in the second display area, and the first pixel circuits include a first transistor, a second transistor, a third transistor, a fourth transistor and at least two first light emitting devices; The control end of the first transistor is electrically connected with a first node, one of a source electrode or a drain electrode of the first transistor is electrically connected with a second node, the other of the source electrode or the drain electrode of the first transistor is electrically connected with a third node, and the second node is electrically connected with the power supply voltage input end; The control end of the second transistor is electrically connected with the scanning signal input end, one of a source electrode or a drain electrode of the second transistor is electrically connected with the data signal input end, and the other of the source electrode or the drain electrode of the second transistor is electrically connected with the second node; The control end of the third transistor is electrically connected with the reset signal control end, one of a source electrode or a drain electrode of the third transistor is electrically connected with the first reset signal input end, and the other of the source electrode or the drain electrode of the third transistor is electrically connected with the first node; The control end of the fourth transistor is electrically connected with the reset signal control end, one of a source electrode or a drain electrode of the fourth transistor is electrically connected with the first reset signal input end, and the other of the source electrode or the drain electrode of the fourth transistor is electrically connected with the third node; Anodes of the two first light emitting devices are electrically connected with the third node. Further, the first pixel circuit further includes: and a fifth transistor having a control terminal electrically connected to the scan signal input terminal, one of a source and a drain electrically connected to the first node, and the other of the source and the drain electrically connected to the third node. Further, the first pixel circuit further includes: a sixth transistor, a control terminal of which is electrically connected to the emission control signal terminal, one of a source or a drain of which is electrically connected to the power supply voltage input terminal, and the other of the source or the drain of which is electrically connected to the second node; and a seventh transistor, a control terminal of the seventh transistor is electrically connected to the emission control signal terminal, one of a source and a drain of the seventh transistor is electrically connected to the third node, and the other of the source and the drain of the seventh transistor is electrically connected to the anode of the first light emitting device. Further, the first pixel circuit further includes a first capacitor, one end of the first capacitor is electrically connected to the power supply voltage in