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CN-117894783-B - Semiconductor packaging structure

CN117894783BCN 117894783 BCN117894783 BCN 117894783BCN-117894783-B

Abstract

The application discloses a semiconductor packaging structure, and relates to the technical field of integrated circuit packaging. The semiconductor packaging structure comprises a lead frame, a first heat conduction layer, a second heat conduction layer, a chip and a plastic package body, wherein the first heat conduction layer is arranged on one surface of the lead frame and comprises first silver powder particles, the second heat conduction layer is arranged on the first heat conduction layer and comprises resin and second silver powder particles, the particle size of the first silver powder particles is smaller than that of the second silver powder particles, the chip is arranged on the second heat conduction layer, the bottom surface and at least part of side walls of the chip are in contact with the second heat conduction layer, and the plastic package body covers the lead frame, the first heat conduction layer, the second heat conduction layer and the chip. The semiconductor packaging structure can avoid or reduce layering.

Inventors

  • CHEN KAI
  • YU JIANMING
  • LI YAN
  • ZHOU LIANG
  • YUAN ANPING
  • GAO HUIQIANG

Assignees

  • 泉州市三安集成电路有限公司

Dates

Publication Date
20260512
Application Date
20231222

Claims (20)

  1. 1. A semiconductor package structure, the semiconductor package structure comprising: A lead frame; the first heat conduction layer is arranged on one surface of the lead frame and comprises first silver powder particles; the second heat conduction layer is arranged on the first heat conduction layer and comprises resin and second silver powder particles, and the particle size of the first silver powder particles is smaller than that of the second silver powder particles; the chip is arranged above the second heat conduction layer, and the bottom surface and at least part of the side wall of the chip are in contact with the second heat conduction layer; And a plastic package body covering the lead frame, the first heat conduction layer, the second heat conduction layer and the chip.
  2. 2. The semiconductor package according to claim 1, wherein the first heat conductive layer is formed by sintering fully sintered silver paste, and wherein the mass ratio of the first silver powder particles in the first heat conductive layer is 95% or more.
  3. 3. The semiconductor package according to claim 1, wherein the mass ratio of the second silver powder particles in the second heat conductive layer is smaller than the mass ratio of the first silver powder particles in the first heat conductive layer.
  4. 4. The semiconductor package structure according to claim 1, wherein the first silver powder particles have a particle size of less than 1 μm and the second silver powder particles have a particle size of 1 μm or more.
  5. 5. The semiconductor package according to claim 1, wherein the particle size of the second silver powder particles is 2 to 20 μm.
  6. 6. The semiconductor package according to claim 1, wherein the second heat conductive layer is formed by sintering semi-sintered silver paste, and the mass ratio of the second silver powder particles in the second heat conductive layer is 85% -98%.
  7. 7. The semiconductor package according to claim 1, wherein the thickness of the first heat conductive layer is 20-200 μm.
  8. 8. The semiconductor packaging structure according to claim 1, wherein the lead frame comprises a base island and a plurality of pins, each pin is located at the periphery of the base island at intervals, the first heat conduction layer is arranged on the base island, an electrode is arranged on the upper surface of the chip and is electrically connected with the pins through leads, and the plastic package body covers the base island and part of the pins and wraps the leads.
  9. 9. The semiconductor package according to claim 8, wherein the leads are provided with first regions, the first regions are regions covered by the plastic package body, and the islands are provided with second regions on sides facing away from the chip, the second regions being regions exposed from the plastic package body.
  10. 10. The semiconductor package according to claim 1, wherein the semiconductor package comprises an electroplated silver layer formed between the first thermally conductive layer and the leadframe.
  11. 11. The semiconductor package according to claim 10, wherein the electroplated silver layer has a thickness of 1.78-7.62 μm.
  12. 12. The semiconductor package according to claim 1, wherein the thermal conductivity of the chip is greater than or equal to 100W/mK.
  13. 13. The semiconductor package according to claim 1, wherein the first heat conductive layer has a first distribution area S1, the second heat conductive layer has a second distribution area S2, the chip has a third distribution area S3, and the first distribution area S1, the second distribution area S2, and the third distribution area S3 satisfy a first formula: 。
  14. 14. the semiconductor package according to claim 1, wherein the second heat conductive layer is formed with a chip coating groove, the chip is embedded in the chip coating groove, a bottom wall of the chip coating groove is in contact with a bottom surface of the chip, and a side wall of the chip coating groove is in contact with a side wall of the chip.
  15. 15. The semiconductor package according to claim 14, wherein the second heat conductive layer has a thickness of 15-185 μm at a portion of the bottom wall of the chip coating groove.
  16. 16. The semiconductor package according to claim 1, wherein the chip has a longitudinal direction and a width direction perpendicular to each other, the chip has a first dimension in the longitudinal direction, the chip has a second dimension in the width direction, and a ratio of the first dimension to the second dimension is 2:1 to 10:1.
  17. 17. The semiconductor package according to claim 16, wherein a ratio of the first dimension to the second dimension is 5.5:1 to 7.5:1.
  18. 18. The semiconductor package according to claim 14, wherein a height of a sidewall of the chip-coating groove is lower than a height of the chip.
  19. 19. The semiconductor package according to claim 14, wherein the height of the sidewalls of the die coating groove is 20% -90% of the height of the die.
  20. 20. The semiconductor package according to claim 1, wherein the second thermally conductive layer covers or exposes an edge of the first thermally conductive layer.

Description

Semiconductor packaging structure Technical Field The application relates to the technical field of integrated circuit packaging, in particular to a semiconductor packaging structure. Background The conventional semiconductor package structure generally comprises a lead frame, a die bond, a chip and a plastic package. The chip is installed on the lead frame through the die bond adhesive, and the chip is bonded with the lead frame, and the plastic package body covers the lead frame, the die bond adhesive and the chip. The existing semiconductor packaging structure is easy to have layering defects. The delamination occurs in the region where the side wall of the chip is located (for example, between the side wall of the chip and the molding compound), the region where the top of the chip is located (for example, between the top of the chip and the molding compound), and the region where the bottom of the chip is located (for example, between the lead frame and the die bond adhesive). Delamination is more likely to occur particularly on high power products, leading to product performance degradation and even failure. Accordingly, there is a need to improve the delamination problem of semiconductor package structures to prevent the failure of the packaged device due to delamination of the chip package product. Disclosure of Invention In view of the above, the present application provides a semiconductor package structure including a leadframe, a first heat conductive layer, a second heat conductive layer, a chip, and a plastic package. The first heat conduction layer is arranged on one surface of the lead frame and comprises first silver powder particles. The second heat conduction layer is arranged on the first heat conduction layer and comprises resin and second silver powder particles, the particle size of the first silver powder particles is smaller than that of the second silver powder particles ., the chip is arranged on the second heat conduction layer, and the bottom surface and at least part of the side wall of the chip are in contact with the second heat conduction layer. The plastic package body covers the lead frame, the first heat conduction layer, the second heat conduction layer and the chip. The silver powder coating has the beneficial effects that compared with the prior art, the silver powder coating has the advantages that the particle size of the first silver powder particles of the first heat conduction layer is smaller than that of the second silver powder particles of the second heat conduction layer, so that the compactness of the first heat conduction layer is better than that of the second heat conduction layer, and the first heat conduction layer has good anti-bending capability. The first heat conduction layer can counteract deformation stress from the lead frame, and layering of the area below the chip can be restrained or avoided. The second heat conduction layer contains resin, and the resin can offset the front stress of the chip in the thickness direction of one step, so that the layering of the area where the top of the chip is located due to the front stress can be reduced. In addition, compared with the first heat conduction layer, the thermal expansion coefficient of the second heat conduction layer containing resin is closer to that of the plastic package body, so that the adhesion between the second heat conduction layer and the plastic package body is better. Therefore, at least part of the side wall of the chip is connected with the plastic package body through the second heat conduction layer, and layering of the area where the side wall of the chip is located can be restrained or avoided. Therefore, through the cooperation of the first heat conduction layer and the second heat conduction layer, layering inside the semiconductor packaging structure can be avoided or reduced. Drawings Fig. 1 is a schematic view of a semiconductor package structure of a first embodiment of the present application; FIG. 2 is an enlarged schematic view of area A of FIG. 1; FIG. 3 is a schematic illustration of the dimensioning of the structure shown in FIG. 1; FIG. 4 is a schematic illustration of the dimensioning of the structure shown in FIG. 2; Fig. 5 is a schematic view of a semiconductor package structure of a second embodiment of the present application; Fig. 6 is a schematic view of a semiconductor package structure prepared in control group 1; fig. 7 is a schematic view of a semiconductor package structure prepared in control group 2; fig. 8 is a C-scan of the first semiconductor package prepared in experimental group 1; FIG. 9 is a T-scan of a first semiconductor package prepared in Experimental group 1; fig. 10 is a slice view of the first semiconductor package prepared in experimental group 1; fig. 11 is a slice view of a second semiconductor package prepared in experimental group 1; Fig. 12 is a slice view of a region of a third semiconductor package prepared in control group 1;