CN-118248693-B - Semiconductor structure and preparation method thereof

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that the first penetrating structure and the second penetrating structure of a three-dimensional memory are poor in electrical connection reliability; the semiconductor device comprises a substrate, a first stacked layer arranged on the substrate, a first penetrating structure arranged in the first stacked layer, an isolation layer arranged on the first stacked layer, a contact pad arranged in the isolation layer, a second side wall structure arranged between the contact pad and the isolation layer, a second barrier layer arranged on the side wall and the bottom surface of the contact pad, and a second penetrating structure arranged on the contact pad and at least partially contacting the contact pad, wherein the bottom size of the contact pad is larger than the top size of the first penetrating structure. The semiconductor structure provided by the application is used for storing data.

Inventors

• CHEN XUANTONG
• CAI JIANCHENG
• ZHOU YANG
• HE XIANGLONG

Assignees

• 福建省晋华集成电路有限公司

Dates

Publication Date

20260505

Application Date

20240430

Claims (18)

1. 1. A semiconductor structure, comprising: A substrate; A first stack layer disposed over the substrate; The first through structure is arranged in the first stacking layer and comprises a first side wall structure, a first barrier layer and a first conductive plug, wherein the first barrier layer and the first conductive plug are arranged on the first side wall structure; An isolation layer disposed over the first stack layer; The contact pad is arranged in the isolation layer and completely covers the first through structure, the contact pad at least partially contacts the first conductive plug, and the contact pad and the first conductive plug are of an integrated structure; The second side wall structure is arranged between the contact pad and the isolation layer; a second barrier layer arranged on the side wall and the bottom surface of the contact pad; The second penetrating structure is arranged on the contact pad and at least partially contacts the contact pad, wherein the bottom size of the contact pad is larger than the top size of the first penetrating structure.
2. 2. The semiconductor structure of claim 1, wherein the first barrier layer is in contact with the first sidewall structure and a portion of the substrate, respectively; The second barrier layer is in contact with the contact pad, the second sidewall structure, and a portion of the first stacked layer, respectively.
3. 3. The semiconductor structure of claim 1 wherein the first barrier layer and the second barrier layer are a unitary structure.
4. 4. The semiconductor structure of claim 3, wherein the first barrier layer is in contact with a portion of a bottom surface of the contact pad and the first conductive plug, respectively.
5. 5. The semiconductor structure of claim 1, wherein the second through structure further comprises a second conductive plug, the contact pad at least partially contacting the second conductive plug.
6. 6. The semiconductor structure of claim 1, wherein the first stacked layer comprises alternating dielectric and conductive layers.
7. 7. The semiconductor structure of claim 1, wherein the first sidewall structure and the second sidewall structure comprise the same layer of material.
8. 8. The semiconductor structure of claim 7, wherein the first and second sidewall structures comprise a metal oxide layer and a third barrier layer disposed in sequence.
9. 9. The semiconductor structure of claim 1, wherein the first through structure, the contact pad, and the second through structure are arranged in a staggered manner.
10. 10. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: A second stacked layer including dielectric layers and conductive layers alternately arranged; the second penetrating structure is located in the second stacked layer.
11. 11. A method of fabricating a semiconductor structure, comprising: Providing a substrate; forming a first stacked layer on the substrate and an isolation layer covering the first stacked layer; Etching the isolation layer and the first stacked layer to form a first channel hole in the first stacked layer respectively, and forming a groove communicated with the first channel hole in the isolation layer, wherein the bottom width of the groove is larger than the top width of the first channel hole; forming a sidewall layer in the first channel hole and the groove; etching the side wall layer to form a first side wall structure arranged in the first channel hole and a second side wall structure arranged in the groove; forming a barrier material layer within the recess and the first channel hole, and the barrier material layer covering the first sidewall structure, the second sidewall structure, and a portion of the first stack layer exposed within the recess; Forming a contact pad and a first conductive plug in the groove and in the first channel hole respectively, wherein the contact pad at least partially contacts the first conductive plug, the contact pad and the first conductive plug are of an integrated structure, the first conductive plug, part of the barrier material layer and the first side wall structure form a first through structure, the contact pad completely covers the first through structure, and the bottom dimension of the contact pad is larger than the top dimension of the first through structure; A second stack layer is formed on the first stack layer, the second stack layer having a second through structure in contact with a portion of the contact pad.
12. 12. The method of manufacturing of claim 11, wherein the etching the isolation layer, the first stacked layer further comprises: forming a first mask pattern on the isolation layer; Etching the isolation layer and the first stacking layer by using the first mask pattern, and forming a first channel hole; Etching the first mask pattern and forming a second mask pattern; and etching the isolation layer by using the second mask pattern to form a groove communicated with the first channel hole in the isolation layer.
13. 13. The method of manufacturing of claim 11, wherein the etching the sidewall layer further comprises: Etching a part of the side wall layer at the bottom of the first channel hole so as to expose a part of the substrate in the first channel hole; and etching part of the side wall layer at the bottom of the groove to expose part of the first stacked layer into the groove and form the first side wall structure and the second side wall structure which are not contacted with each other.
14. 14. The method of manufacturing of claim 13, wherein the forming a layer of barrier material within the recess and the first channel hole comprises: The barrier material layer is deposited within the recess and the first channel hole, the barrier material layer covering the first sidewall structure, the second sidewall structure, the substrate partially exposed within the channel hole, and the first stack layer partially exposed within the recess.
15. 15. The method of manufacturing of claim 13, wherein the barrier material layer further comprises a first barrier layer covering the first sidewall structure and a second barrier layer covering the second sidewall structure.
16. 16. The method of manufacturing of claim 11, wherein the forming sidewall layers within the first channel hole and the recess further comprises: and sequentially depositing a metal oxide layer and a third barrier layer in the first channel hole and the groove, wherein the metal oxide layer and the third barrier layer form the side wall layer.
17. 17. The method of manufacturing of claim 11, wherein the first through structures, the contact pads, and the second through structures are arranged in a staggered manner.
18. 18. The method of manufacturing of claim 15, wherein the first conductive plug is in contact with the first barrier layer.

Description

Semiconductor structure and preparation method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. Background With the development of semiconductor memory devices, the demand for semiconductor memory devices having high-density data memory cells is also continuously increasing, and thus, three-dimensional memories having vertically stacked data memory cell layers are becoming a hot spot of research. The three-dimensional memory comprises a substrate and a plurality of laminated structures stacked on the substrate. For example, a first laminated structure and a second laminated structure are stacked on a substrate, the first laminated structure at the upper part comprises a first penetrating structure, the second laminated structure at the lower part comprises a second penetrating structure, and the top of the first penetrating structure is contacted with and electrically connected with the bottom of the second penetrating structure. However, in the three-dimensional memory, the reliability of the electrical connection between the first through structure and the second through structure is poor, which reduces the yield of the three-dimensional memory. Disclosure of Invention In view of the above, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can improve the yield of a three-dimensional memory. In order to achieve the above object, the embodiment of the present application provides the following technical solutions: The first aspect of the embodiment of the application provides a semiconductor structure, which comprises a substrate, a first stacked layer, a first penetrating structure, a isolation layer, a contact pad, a second side wall structure and a second barrier layer, wherein the first stacked layer is arranged on the substrate, the first penetrating structure is arranged in the first stacked layer and comprises a first side wall structure and a first barrier layer arranged on the first side wall structure, the isolation layer is arranged on the first stacked layer, the contact pad is arranged in the isolation layer and completely covers the first penetrating structure, the second side wall structure is arranged between the contact pad and the isolation layer, the second barrier layer is arranged on the side wall and the bottom surface of the contact pad, and the second penetrating structure is arranged on the contact pad and at least partially contacts the contact pad, wherein the bottom size of the contact pad is larger than the top size of the first penetrating structure. In an alternative embodiment, the first barrier layer is in contact with the first sidewall structure and a portion of the substrate, respectively, and the second barrier layer is in contact with the contact pad, the second sidewall structure, and a portion of the first stack layer, respectively. In an alternative embodiment, the first barrier layer and the second barrier layer are a unitary structure. In an alternative embodiment, the first through structure further comprises a first conductive plug, the contact pad at least partially contacting the first conductive plug. In an alternative embodiment, the contact pad is of unitary construction with the first conductive plug. In an alternative embodiment, the first barrier layer is in contact with a portion of the bottom surface of the contact pad and the first conductive plug. In an alternative embodiment, the second through structure further comprises a second conductive plug, the contact pad at least partially contacting the second conductive plug. In an alternative embodiment, the first stacked layer includes alternating dielectric and conductive layers. In an alternative embodiment, the first sidewall structure and the second sidewall structure comprise the same layer of material. In an alternative embodiment, the first sidewall structure and the second sidewall structure include a metal oxide layer and a second barrier layer disposed in sequence. In an alternative embodiment, the first penetrating structure, the contact pad, and the second penetrating structure are arranged in a staggered manner. In an alternative embodiment, the semiconductor structure further comprises a second stacked layer comprising alternating dielectric layers and conductive layers, the second through structure being located within the second stacked layer. A second aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: Providing a substrate; forming a first stacked layer on the substrate and an isolation layer covering the first stacked layer; Etching the isolation layer and the first stacked layer to form a first channel hole in the first stacked layer respectively, and forming a groove communicated with the first channel hole in the isolation la