CN-118316449-B - Static characteristic built-in self-test circuit of high-precision ADC (analog to digital converter)

CN118316449BCN 118316449 BCN118316449 BCN 118316449BCN-118316449-B

Abstract

The invention provides a built-in self-test circuit for static characteristics of a high-precision ADC (analog-to-digital converter), which comprises the steps of sampling an input external common-mode signal Vcm to obtain a sampling common-mode signal in a sampling and holding stage, sampling and amplifying the sampling common-mode signal according to a positive input end signal Vip and reducing output impedance to obtain a first amplified common-mode signal in a first quantization stage, sampling and amplifying the sampling common-mode signal according to a negative input end signal Vin and reducing output impedance to obtain a second amplified common-mode signal in a second quantization stage, wherein the positive input end signal Vip and the negative input end signal Vin are a pair of differential signals, quantizing the first amplified common-mode signal and the second amplified common-mode signal, and averaging quantized results of the first amplified common-mode signal and the second amplified common-mode signal to obtain a high-precision test signal. In the invention, the sampling common mode signal is quantized according to a pair of differential signals, and the result of the two times of quantization is summed, so that the sampling thermal noise is eliminated.

Inventors

ZHU ZHANGMING
HUANG YIYAO
ZHANG YANBO
FU GUOLONG
LIU SHUBIN

Assignees

西安电子科技大学

Dates

Publication Date: 20260505
Application Date: 20240418

Claims (9)

1. A high-precision ADC static characteristic built-in self-test circuit, comprising: In a sample-hold stage, sampling an input external common-mode signal Vcm to obtain a sampling common-mode signal; in the first quantization stage, sampling and amplifying the sampling common-mode signal according to a positive input end signal Vip, and reducing output impedance to obtain a first amplified common-mode signal; In a second quantization stage, sampling and amplifying the sampling common-mode signal according to a negative input end signal Vin, and reducing output impedance to obtain a second amplified common-mode signal, wherein the positive input end signal Vip and the negative input end signal Vin are a pair of differential signals; The static characteristic built-in self-test circuit comprises a noise elimination circuit, an operational amplification circuit, a negative capacitance circuit, a load circuit, a clock signal generation module and a signal redistribution module; the clock signal generation module is used for periodically quantifying and controlling the static characteristic built-in self-test circuit; The noise elimination circuit is used for carrying out voltage reset processing on the sampling capacitor, and carrying out periodic sampling on the external common-mode signal Vcm under the condition of voltage reset of the sampling capacitor to obtain a sampling common-mode signal; The negative capacitance circuit is used for gain compensation of the operational amplification circuit; The operational amplification circuit is used for carrying out signal amplification processing on the differential pressure signal under the action of gain compensation to obtain an amplified fully differential signal; The signal redistribution module is used for distributing the amplified fully-differential signal into sub-amplified fully-differential signals and inputting the sub-amplified fully-differential signals into branches in the load circuit; The load circuit is used for carrying out noise elimination on the sub-amplification full-differential signals, carrying out sampling average processing on the sub-amplification common-mode signals in each period in each branch, and summing the sub-amplification common-mode signals subjected to sampling average processing in a plurality of branches to obtain high-precision test signals, wherein the load circuit carries out noise elimination on the sub-amplification full-differential signals by controlling the accessed bandwidth.
2. The static feature built-in self-test circuit of a high-precision ADC of claim 1, wherein the bandwidth of said negative capacitance circuit is smaller than the bandwidth of said operational amplifier circuit.
3. The built-in self-test circuit for static characteristics of a high-precision ADC according to claim 1, wherein a first output terminal of the noise cancellation circuit is connected to a first input terminal of the operational amplification circuit and an input terminal of the negative capacitance circuit, respectively, a second output terminal of the noise cancellation circuit is connected to a second input terminal of the operational amplification circuit and an input terminal of the negative capacitance circuit, respectively, a first output terminal of the operational amplification circuit is connected to a first input terminal of the signal redistribution module, a second output terminal of the operational amplification circuit is connected to a second input terminal of the signal redistribution module, a first input terminal of the signal redistribution module is connected to a first input terminal of the load circuit, a second input terminal of the signal redistribution module is connected to a second input terminal of the load circuit, and the clock signal generation module is connected to input terminals of all switches in the built-in self-test circuit for static characteristics.
4. The static characteristic built-in self-test circuit of the high-precision ADC as set forth in claim 1, wherein the noise cancellation circuit comprises a switch S 11 , a switch S 12 , a switch S 21 , a switch S 22 , a switch S 31 , a switch S 32 , a switch S 41 , a switch S 42 , a switch CTL1, a switch CTL2, a switch CH1, a switch CH2, a switch CHb1, a switch CHb2, a capacitor C S1 , a capacitor C S2 , a capacitor C OS1 and a capacitor C OS2 ; One end of the switch CH1, the positive input end signal Vip and one end of the switch CHb2 are connected with each other, the other end of the switch CH1, the other end of the switch CHb1, one end of the switch S 21 and the upper polar plate of the capacitor C S1 are connected with each other, the other end of the switch CH2, the other end of the switch CHb2, the other end of the switch S 22 and the upper polar plate of the capacitor C S2 are connected with each other, one end of the switch CH2, A negative input terminal signal Vin and one end of the switch CHb1 are connected to each other, the other end of the switch S 21 , the external common-mode signal Vcm and one end of the switch S 22 are connected to each other, the other end of the switch S 11 , The external common mode signal Vcm and one end of the switch S 12 are connected with each other, the lower polar plate of the capacitor C S1 , one end of the switch S 11 , the other end of the switch CTL1, The first input end of the operational amplifier circuit and the input end of the negative capacitance circuit are connected with each other, one end of the switch S 31 is connected with the power voltage Vref, one end of the switch S 41 is connected with the external common mode signal Vcm, the other end of the switch S 31 , The other end of the switch S 41 is connected with the upper polar plate of the capacitor C OS1 , the lower polar plate of the capacitor C OS1 is connected with one end of the switch CTL1, the lower polar plate of the capacitor C S2 , the other end of the switch S 12 , one end of the switch CTL2, the second input terminal of the operational amplifier circuit, and the input terminal of the negative capacitance circuit are connected to each other.
5. The self-test circuit for static characteristics of a high-precision ADC as claimed in claim 4, wherein said operational amplifier circuit comprises an operational amplifier A 1 , a switch S 23 , a switch S 24 , a capacitor C f11 and a capacitor C f12 ; The upper polar plate of the capacitor C f11 and the negative input end of the operational amplifier A 1 are both connected with the first input end of the operational amplifier circuit, and the upper polar plate of the capacitor C f12 and the positive input end of the operational amplifier A 1 are both connected with the second input end of the operational amplifier circuit; the lower electrode plate of the capacitor C f11 , the other end of the switch S 23 , the negative output end of the operational amplifier a 1 and the first input end of the signal redistribution module are connected with each other, the lower electrode plate of the capacitor C f12 , the other end of the switch S 24 , the positive output end of the operational amplifier a 1 and the second input end of the signal redistribution module are connected with each other, and one end of the switch S 23 and one end of the switch S 24 are connected with the external common mode signal Vcm.
6. The self-test circuit for static characteristics of a high-precision ADC as claimed in claim 5, wherein said signal redistribution module comprises a switch CH3, a switch CH4, a switch CHb3 and a switch CHb4; The first input end of the signal redistribution module is connected with one end of the switch CH3 and one end of the switch CHb3 respectively, the second input end of the signal redistribution module is connected with one end of the switch CH4 and one end of the switch CHb4 respectively, the other end of the switch CH3, the other end of the switch CHb4 and the first input end of the load circuit are connected with each other, and the other end of the switch CH4, the other end of the switch CHb3 and the second input end of the load circuit are connected with each other.
7. The self-test circuit for static characteristics of a high-precision ADC as set forth in claim 6, wherein said load circuit comprises a switch S 51 , a switch S 52 , a capacitor C sar1 , a capacitor C sar2 , a resistor R 1 , a resistor R 2 , a switch S 61 and a switch S 62 ; The first input end of the load circuit is connected with one end of the switch S 51 , the other end of the switch S 51 is connected with the upper electrode plate of the capacitor C sar1 , the lower electrode plate of the capacitor C sar1 , one end of the switch S 61 and one end of the resistor R 1 are connected with each other, the other end of the switch S 61 and the other end of the resistor R 1 are grounded at the same time, the second input end of the load circuit is connected with one end of the switch S 52 , the other end of the switch S 52 is connected with the upper electrode plate of the capacitor C sar2 , the lower electrode plate of the capacitor C sar2 , one end of the switch S 62 and one end of the resistor R 2 are connected with each other, and the other end of the switch S 62 and the other end of the resistor R 2 are grounded at the same time.
8. The circuit of claim 7, wherein the clock signal generation module is configured to generate a first periodic quantization clock signal, a second periodic quantization clock signal, a third periodic quantization clock signal, a fourth periodic quantization clock signal, a fifth periodic quantization clock signal, a sixth periodic quantization clock signal, a seventh periodic quantization clock signal, and an eighth periodic quantization clock signal; The first periodic quantization clock signal is used to control switch S 11 and switch S 12 , the second periodic quantization clock signal is used to control switch S 21 -S 24 , the third periodic quantization clock signal is used to control switch S 31 and switch S 32 , the fourth periodic quantization clock signal is used to control switch S 41 and switch S 42 , the fifth periodic quantization clock signal is used to control switch S 51 and switch S 52 , the sixth periodic quantization clock signal is used to control switch S 61 and switch S 62 , the seventh periodic quantization clock signal is used to control switches CH 1-CH 4, and the eighth periodic quantization clock signal is used to control switches CHb 1-CHb 4.
9. The self-test circuit for static characteristics of a high-precision ADC as recited in claim 7, wherein the test signal collected by the capacitor C sar1 is: ; Wherein, the Representing the test signal collected by the capacitor C sar1 , Representing the supply voltage of the power supply, Representing the noise voltage at which the bottom plate of capacitor C S1 is fixed.

Description

Static characteristic built-in self-test circuit of high-precision ADC (analog to digital converter) Technical Field The invention belongs to the technical field of integrated circuit design, and particularly relates to a static characteristic built-in self-test circuit of a high-precision ADC. Background The conventional built-in self-test circuit requires an input of a high linearity test signal, for example, an 18bit ADC under test requires a linearity of the test signal of 21 bits. Most of the existing mainstream schemes adopt a traditional error elimination test algorithm, so that the linearity requirement of input signals of the ADC to be tested can be relieved. However, the conventional scheme also puts high demands on the linearity of the voltage offset of the two input signals when testing high-precision ADCs. In addition, when the traditional method is used for testing the static characteristics of the high-precision ADC, the test signal generally needs higher precision compared with the test signal of the common-precision ADC. Taking a 24-bit high-precision ADC as an example, 2 24 -1=16777215 code value intervals need to be tested. 10 points are sampled per code value interval, then a total of 1.6 hundred million samples are required. And the ADC to be tested needs to repeatedly sample each sampling point for tens of times so as to reduce the influence of noise on the histogram test result. Obviously, the conventional test method occupies extremely large storage space and test time when testing the high-precision ADC, so that the implementation process is difficult and huge resource expenditure is generated. Therefore, the existing built-in self-test circuit has the technical problems of higher requirement on the linearity of the test signal and large data storage space. Disclosure of Invention In order to solve the above problems in the prior art, the present invention provides a high-precision self-test circuit with built-in static characteristics for ADC. The technical problems to be solved by the invention are realized by the following technical scheme: the invention provides a high-precision ADC static characteristic built-in self-test circuit, which comprises: In a sample-hold stage, sampling an input external common-mode signal Vcm to obtain a sampling common-mode signal; in the first quantization stage, sampling and amplifying the sampling common-mode signal according to the positive input end signal Vip, and reducing output impedance to obtain a first amplified common-mode signal; in the second quantization stage, sampling and amplifying the sampling common-mode signal according to the negative input end signal Vin, and reducing the output impedance to obtain a second amplified common-mode signal, wherein the positive input end signal Vip and the negative input end signal Vin are a pair of differential signals, and the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the first amplified common-mode signal and the second amplified common-mode signal are summed to obtain a high-precision test signal. Optionally, the static characteristic built-in self-test circuit comprises a noise elimination circuit, an operational amplification circuit, a negative capacitance circuit, a load circuit, a clock signal generation module and a signal redistribution module; the clock signal generation module is used for periodically and quantitatively controlling the static characteristic built-in self-test circuit; The noise elimination circuit is used for carrying out voltage reset processing on the sampling capacitor, and carrying out periodic sampling on an external common mode signal Vcm under the condition of voltage reset of the sampling capacitor to obtain a sampling common mode signal; the negative capacitance circuit is used for gain compensation of the operational amplification circuit; the operational amplification circuit is used for carrying out signal amplification processing on the differential pressure signal under the action of gain compensation to obtain an amplified fully differential signal; The signal redistribution module is used for distributing the amplified fully-differential signals into sub-amplified fully-differential signals and inputting the sub-amplified fully-differential signals into branches in the load circuit; The load circuit is used for carrying out noise elimination on the sub-amplified full-differential signals, carrying out sampling and average processing on the sub-amplified common-mode signals in each period in each branch, and summing the sub-amplified common-mode signals after the sampling and average processing in a plurality of branches to obtain high-precision test signals, wherein the load circuit carries out noise elimination on the sub-amplified full-differential signals by controlling the accessed bandwidth. Optionally, the bandwidth of the negative capacitance circuit is smaller t