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CN-118353427-B - High-speed zero-crossing comparator with low walking error and control method thereof

CN118353427BCN 118353427 BCN118353427 BCN 118353427BCN-118353427-B

Abstract

The application discloses a high-speed zero-crossing comparator with low walking error and a control method thereof, wherein the high-speed zero-crossing comparator comprises a differential amplifier module, a five-tube operational amplifier module, a hysteresis control module and a driving-stage circuit, the output end of the differential amplifier module is connected with the output end of the five-tube operational amplifier module in a first connection point, the first connection point is respectively connected with the input end of the driving stage circuit and the input end of the hysteresis control module, and the output end of the hysteresis control module is connected with the input end of the differential amplifier module. The embodiment of the application can enhance the processing capability of the comparator on input signals with different slew rates and overdrive under the condition of consuming smaller static power consumption, and reduce propagation delay spread under the wide input slew rate and overdrive, thereby reducing drift error and kickback noise of zero crossing points of the high-speed zero-crossing comparator. The application can be widely applied to the technical field of integrated circuits.

Inventors

  • GUO JIANPING
  • ZHU JUNJIE

Assignees

  • 中山大学

Dates

Publication Date
20260505
Application Date
20240513

Claims (9)

  1. 1. The utility model provides a high-speed zero-crossing comparator of low walking error, its characterized in that, high-speed zero-crossing comparator includes differential amplifier module, five-tube operational amplifier module, hysteresis control module and drive level circuit, differential amplifier module's output with five-tube operational amplifier module's output is connected in first junction point, first junction point respectively with drive level circuit's input with hysteresis control module's input is connected, hysteresis control module's output with differential amplifier module's input is connected, wherein: The differential amplifier module is used for acquiring differential input signals, amplifying and converting the differential input signals and outputting single-ended signals, and comprises a hysteresis control full-differential amplifier, a small-gain high-bandwidth full-differential amplifier module, a judging circuit and a differential input single-ended output amplifier, wherein the output end of the hysteresis control full-differential amplifier is connected with the input end of the small-gain high-bandwidth full-differential amplifier module, the output end of the small-gain high-bandwidth full-differential amplifier module is connected with the input end of the judging circuit, and the output end of the judging circuit is connected with the input end of the differential input single-ended output amplifier; The five-tube operational amplifier module is used for acquiring the differential input signal and amplifying the differential input signal to generate a current signal related to the slew rate of the differential input signal; the hysteresis control module is used for controlling the positive and negative hysteresis threshold of the differential amplifier module; The driving stage circuit is used for carrying out output driving processing according to the single-ended signal and the current signal and outputting a digital signal containing phase information.
  2. 2. The high-speed zero-crossing comparator according to claim 1, wherein the hysteresis control fully differential amplifier is configured to acquire the differential input signal and amplify the differential input signal to output a differential signal after primary amplification; The small-gain high-bandwidth full-differential amplifier module comprises a first small-gain high-bandwidth full-differential amplifier, a second small-gain high-bandwidth full-differential amplifier, a third small-gain high-bandwidth full-differential amplifier, a fourth small-gain high-bandwidth full-differential amplifier and a fifth small-gain high-bandwidth full-differential amplifier, and is used for carrying out step-by-step amplification processing on the differential signals amplified by the first stage and outputting differential signals amplified by six stages; The judging circuit is used for comparing and latching the six-stage amplified differential signals and outputting the compared differential signals; the differential input single-ended output amplifier is used for converting the compared differential signals and outputting the single-ended signals.
  3. 3. The high-speed zero-crossing comparator according to claim 2, wherein the hysteresis control fully differential amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, and a second resistor, wherein a gate of the first transistor is connected to the hysteresis control module, a source of the first transistor, a source of the second transistor, a source of the seventh transistor, a source of the eighth transistor are each connected to the first small-gain high-bandwidth fully differential amplifier and connected in parallel with a high level, a drain of the first transistor, a drain of the second transistor are each connected to a source of the third transistor, the drain of the third transistor, the gate of the third transistor, and the drain of the fourth transistor are all connected to the first small-gain high-bandwidth fully differential amplifier, the drain of the seventh transistor and the drain of the eighth transistor are all connected to the source of the sixth transistor, the gate of the sixth transistor, the drain of the fifth transistor are all connected to the first small-gain high-bandwidth fully differential amplifier, the source of the fourth transistor is connected to the source of the fifth transistor and to ground, the gate of the fourth transistor is connected to the first differential input signal, the gate of the fifth transistor is connected to the second differential input signal, the gate of the second transistor is connected to the first end of the first resistor, the second end of the first resistor is grounded, the gate of the seventh transistor is connected to the first end of the second resistor, the second end of the second resistor is grounded.
  4. 4. The high-speed zero-crossing comparator according to claim 2, wherein the first small-gain high-bandwidth fully-differential amplifier, the second small-gain high-bandwidth fully-differential amplifier, the third small-gain high-bandwidth fully-differential amplifier, the fourth small-gain high-bandwidth fully-differential amplifier, and the fifth small-gain high-bandwidth fully-differential amplifier each have the same structure, the first small-gain high-bandwidth fully-differential amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein a source of the ninth transistor is connected to a source of the twelfth transistor, a gate of the ninth transistor, a drain of the ninth transistor is connected to a drain of the tenth transistor, a gate of the twelfth transistor, a drain of the twelfth transistor is connected to a drain of the eleventh transistor, and a source of the tenth transistor is connected to a source of the eleventh transistor.
  5. 5. The high speed zero crossing comparator of claim 2, wherein the decision circuit comprises a twenty-ninth transistor, a thirty-third transistor, a thirty-first transistor, a thirty-third transistor, and a thirty-fourth transistor, wherein a source of the twenty-ninth transistor is connected to a source of the thirty-fourth transistor, a gate of the twenty-ninth transistor is connected to the fifth small gain high bandwidth fully differential amplifier, a gate of the thirty-fourth transistor is connected to the fifth small gain high bandwidth fully differential amplifier, a drain of the twenty-ninth transistor, a gate of the thirty-fourth transistor, a drain of the thirty-first transistor, a gate of the thirty-third transistor, a drain of the thirty-fourth transistor, a single ended output of the thirty-fourth transistor, a drain of the thirty-first transistor, a gate of the thirty-third transistor, a drain of the thirty-fourth transistor, a gate of the thirty-third transistor, a single ended output of the thirty-third transistor, a source of the thirty-third transistor, and a source of the thirty-third transistor are all connected to the differential input amplifier.
  6. 6. The high-speed zero-crossing comparator of claim 2, wherein the differential input single-ended output amplifier comprises a thirty-fifth transistor, a thirty-sixth transistor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, and a fortieth transistor, wherein the sources of the thirty-seventh transistor are connected to the decision circuit and the drive stage circuit, respectively, the gates of the thirty-seventh transistor, the drain of the thirty-fifth transistor, the drain of the thirty-sixth transistor, and the gate of the thirty-eighth transistor are each connected to the source of the thirty-ninth transistor, the gates of the thirty-fifth transistor, the gates of the thirty-sixth transistor are each connected to the decision circuit, the gates of the thirty-ninth transistor, the gates of the fortieth transistor are each connected to the decision circuit, the drains of the thirty-seventh transistor, the drain of the fortieth transistor, and the drain of the drive stage circuit are each connected to the source of the thirty-eighth transistor, and the source of the thirty-eighth transistor are each connected to the drain of the thirty-eighth transistor.
  7. 7. The high-speed zero-crossing comparator of claim 2, wherein the five-pipe operational amplifier module comprises a first five-pipe operational amplifier, a second five-pipe operational amplifier, a third five-pipe operational amplifier, a fourth five-pipe operational amplifier, and a fifth five-pipe operational amplifier, the first five-pipe operational amplifier, the second five-pipe operational amplifier, the third five-pipe operational amplifier, the fourth five-pipe operational amplifier, and the fifth five-pipe operational amplifier being sequentially connected, the first five-pipe operational amplifier, the second five-pipe operational amplifier, the third five-pipe operational amplifier, the fourth five-pipe operational amplifier, and the fifth five-pipe operational amplifier having the same structure, the first five-pipe operational amplifier comprising a fiftieth transistor, and an fiftieth transistor, the source of the fifty-fifth transistor is connected with the source of the fifty-eighth transistor in parallel, the grid of the fifty-fifth transistor and the drain of the fifty-seventh transistor are connected with the drain of the fifty-sixth transistor, the drain of the fifty-eighth transistor and the drain of the fifty-seventh transistor are connected and then serve as the output end of the first five-transistor operational amplifier, the output end of the first five-transistor operational amplifier is connected with the non-inverting output end of the first small-gain high-bandwidth fully-differential amplifier, the grid of the fifty-seventh transistor is connected with the first differential input signal, the grid of the fifty-seventh transistor is connected with the second differential input signal, and the source of the fifty-sixth transistor and the source of the fifty-seventh transistor are connected with ground.
  8. 8. The high speed zero crossing comparator of claim 2, wherein the hysteresis control module comprises a fifty-first transistor, a fifty-third transistor, and a fifty-fourth transistor, a source of the fifty-first transistor being connected to a source of the fifty-third transistor and connected in parallel high, a drain of the fifty-first transistor, a drain of the fifty-third transistor each being connected to the hysteresis control fully differential amplifier, a gate of the fifty-first transistor, a gate of the fifth-twelfth transistor, a drain of the thirteenth transistor, a drain of the fifty-fourth transistor each being connected to the hysteresis control fully differential amplifier, a source of the fifty-third transistor being connected to a source of the fifty-fourth transistor and connected to ground, a gate of the fifty-third transistor each being connected to the differential input single ended output amplifier.
  9. 9. The high-speed zero-crossing comparator according to claim 6, wherein the driving stage circuit includes a first stage driving unit, a second stage driving unit, a third stage driving unit, a fourth stage driving unit, and a fifth stage driving unit, the first stage driving unit being connected to the second stage driving unit and the third stage driving unit, respectively, the second stage driving unit being connected to the fourth stage driving unit, the third stage driving unit being connected to the fifth stage driving unit, the first stage driving unit, the second stage driving unit, the third stage driving unit, the fourth stage driving unit, and the fifth stage driving unit having the same structure, the first stage driving unit including a fortieth transistor whose gates are connected to the drain of the thirty-ninth transistor, whose sources are connected to a high level, and a fortieth transistor whose sources are connected to ground, and a fortieth transistor whose drains are connected to the fourth stage driving unit and the drain of the fortieth transistor, respectively.

Description

High-speed zero-crossing comparator with low walking error and control method thereof Technical Field The application relates to the technical field of integrated circuits, in particular to a high-speed zero-crossing comparator with low walking error and a control method thereof. Background The existing method is based on a comparator in a laser radar time discrimination method, only considers the influence of the overdrive voltage of an input signal of the comparator on propagation delay spread, ignores the influence of the slew rate of the input signal on propagation delay spread, and has more obvious influence than the overdrive voltage in time discrimination. While some methods consider both slew rate and overdrive voltage effects, the delay spread is still a few hundred ps when the slew rate of the input signal varies over a wide range. There is also a method of amplifying an input signal in multiple stages until saturation, so that the speed of signals having different slew rates and overdrive voltages is increased to be the same, thereby reducing a walking error, but the static power consumption is high. In summary, the technical problems in the related art are to be improved. Disclosure of Invention The embodiment of the application mainly aims to provide a high-speed zero-crossing comparator with low walking error and a control method thereof, which can enhance the processing capability of the comparator on input signals with different slew rates and overdrive under the condition of consuming smaller static power consumption, and reduce propagation delay spread under wide input slew rate and overdrive, thereby reducing drift error and kickback noise of zero crossing points of the high-speed zero-crossing comparator. In order to achieve the above object, an aspect of the embodiments of the present application provides a high-speed zero-crossing comparator with low walking error, the high-speed zero-crossing comparator includes a differential amplifier module, a five-tube operational amplifier module, a hysteresis control module and a driving stage circuit, wherein an output end of the differential amplifier module is connected to a first connection point with an output end of the five-tube operational amplifier module, the first connection point is respectively connected to an input end of the driving stage circuit and an input end of the hysteresis control module, and an output end of the hysteresis control module is connected to an input end of the differential amplifier module, wherein: the differential amplifier module is used for acquiring differential input signals, amplifying and converting the differential input signals and outputting single-ended signals; The five-tube operational amplifier module is used for acquiring the differential input signal and amplifying the differential input signal to generate a current signal related to the slew rate of the differential input signal; the hysteresis control module is used for controlling the positive and negative hysteresis threshold of the differential amplifier module; The driving stage circuit is used for carrying out output driving processing according to the single-ended signal and the current signal and outputting a digital signal containing phase information. In some embodiments, the differential amplifier module includes a hysteresis control full-differential amplifier, a small-gain high-bandwidth full-differential amplifier module, a decision circuit, and a differential input single-ended output amplifier, where an output end of the hysteresis control full-differential amplifier module is connected to an input end of the small-gain high-bandwidth full-differential amplifier module, an output end of the small-gain high-bandwidth full-differential amplifier module is connected to an input end of the decision circuit, and an output end of the decision circuit is connected to an input end of the differential input single-ended output amplifier, where: the hysteresis control full differential amplifier is used for acquiring the differential input signal and amplifying the differential input signal to output a differential signal after primary amplification; The small-gain high-bandwidth full-differential amplifier module comprises a first small-gain high-bandwidth full-differential amplifier, a second small-gain high-bandwidth full-differential amplifier, a third small-gain high-bandwidth full-differential amplifier, a fourth small-gain high-bandwidth full-differential amplifier and a fifth small-gain high-bandwidth full-differential amplifier, and is used for carrying out step-by-step amplification processing on the differential signals amplified by the first stage and outputting differential signals amplified by six stages; The judging circuit is used for comparing and latching the six-stage amplified differential signals and outputting the compared differential signals; the differential input single-ended output amplifier is used for conve