CN-118398664-B - Semiconductor structure and preparation method thereof

CN118398664BCN 118398664 BCN118398664 BCN 118398664BCN-118398664-B

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that the performance of the semiconductor structure cannot be guaranteed due to the fact that the semiconductor structure is reduced along with the size reduction; the channel layer is positioned between the source electrode layer and the drain electrode layer; the gate structure is positioned on the side wall of the channel layer, the gate dielectric layer is positioned between the gate structure and the channel layer, and a part of dielectric layer is arranged between the source layer and the gate structure, wherein the source layer is provided with a plurality of depressions extending towards one side of the substrate, and the channel layer is partially filled in the depressions and is electrically connected with the source layer. The application is used for reducing the size of the semiconductor structure and improving the performance of the semiconductor structure.

Inventors

ZHANG DING
Lu Yanduan
YOU JINGJING
LIU WEITING

Assignees

福建省晋华集成电路有限公司

Dates

Publication Date: 20260508
Application Date: 20240423

Claims (12)

1. A semiconductor structure, comprising: A substrate; A source layer and a drain layer stacked on the substrate; A channel layer between the source layer and the drain layer; a gate structure located on the sidewall of the channel layer; A gate dielectric layer between the gate structure and the channel layer; The dielectric layer is partially arranged between the source electrode layer and the grid electrode structure; Wherein the source electrode layer is provided with a plurality of depressions extending towards one side of the substrate; A filling layer located between the channel layer and the drain layer and filling the recess; the filling layer comprises a first part and a second part, the first part is positioned above the second part and is in contact with the second part, and the maximum width W2 of the second part is smaller than the maximum width W1 of the first part; the filling layer further comprises a third part, wherein the second part is positioned between the first part and the third part, and the maximum width W3 of the third part is larger than the maximum width W2 of the second part; The channel layer is partially arranged between the third part and the source electrode layer and is electrically connected with the source electrode layer.
2. The semiconductor structure of claim 1, wherein the recess has a contour shape that is one of an arcuate structure or a U-shaped structure.
3. The semiconductor structure of claim 1, wherein a maximum width W3 of the third portion is less than a maximum width W1 of the first portion.
4. The semiconductor structure of claim 1, wherein the gate dielectric layer comprises a first dielectric portion and a second dielectric portion connected to each other, the second dielectric portion being in direct contact with the channel layer.
5. The semiconductor structure of claim 4, wherein the second dielectric portion is in direct contact with the source layer.
6. The semiconductor structure of claim 4, wherein the second dielectric portion is located above the source layer with a portion of the dielectric layer between the second dielectric portion and the source layer.
7. The semiconductor structure of claim 1, wherein the gate dielectric layer has an L-shaped profile.
8. The semiconductor structure of claim 1, further comprising a sacrificial layer between the gate dielectric layer and the channel layer, the sacrificial layer having an L-shaped profile.
9. The semiconductor structure of claim 4, wherein sidewalls of the first dielectric portion are in direct contact with the dielectric layer.
10. A method of fabricating a semiconductor structure, comprising: providing a substrate, and forming a source electrode layer on the substrate; Forming a dielectric layer on the source electrode layer, and forming a gate dielectric layer in the dielectric layer; forming a gate structure on a sidewall of the gate dielectric layer; Forming a recess extending towards one side of the substrate on the source layer, and forming a channel layer so that the channel layer partially fills the recess, wherein the channel layer is electrically connected with the source layer, and depositing an insulating filling material on the channel layer to form a filling layer; Forming a drain layer on the channel layer and the filling layer; The filling layer comprises a first part and a second part, wherein the first part is positioned above the second part and is in contact with the second part, the maximum width W2 of the second part is smaller than the maximum width W1 of the first part, the filling layer further comprises a third part, the second part is positioned between the first part and the third part, and the maximum width W3 of the third part is larger than the maximum width W2 of the second part.
11. The method of claim 10, wherein the method of forming the gate dielectric layer and the gate structure comprises: forming a plurality of initial grid electrodes on the dielectric layer, wherein the initial grid electrodes are arranged on the dielectric layer at intervals along the horizontal direction, and an isolation structure is formed between adjacent initial grid electrodes; Forming a first opening extending along the vertical direction in the initial grid, wherein the first opening penetrates through one side, away from the source electrode layer, of the dielectric layer, the first opening does not expose the source electrode layer, and the reserved initial grid is formed into a grid structure; a gate dielectric layer is formed over the first opening.
12. The method of claim 10, wherein the forming a recess on the source layer and the forming a channel layer comprises: removing part of the dielectric layer and part of the source electrode layer to form a through hole penetrating through the dielectric layer at the center of the gate dielectric layer; removing part of the source electrode layer along the etching direction of the through hole so as to form a recess communicated with the through hole on the source electrode layer; And forming a channel layer on the exposed surfaces of the through hole and the recess.

Description

Semiconductor structure and preparation method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. Background With the development of semiconductor technology, semiconductor integrated circuits tend to be designed in a smaller size and arranged in a higher density, and for smaller and smaller semiconductor structures, it is more difficult to further reduce the size and ensure the performance of the semiconductor structures. Since the conventional Planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continuously shrink, how to improve the conventional Planar MOS transistor, thereby reducing the geometry of the MOS transistor and/or improving the performance of the transistor element has become a technical problem to be solved. Disclosure of Invention In view of the foregoing, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which are used for reducing the size of the semiconductor structure and improving the performance of the semiconductor structure. In order to achieve the above object, the embodiment of the present application provides the following technical solutions: The first aspect of the embodiment of the application provides a semiconductor structure, which comprises a substrate, a source electrode layer, a drain electrode layer, a channel layer, a grid electrode structure, a grid electrode dielectric layer and a dielectric layer, wherein the source electrode layer and the drain electrode layer are stacked on the substrate, the channel layer is positioned between the source electrode layer and the drain electrode layer, the grid electrode structure is positioned on the side wall of the channel layer, the grid electrode dielectric layer is positioned between the grid electrode structure and the channel layer, a part of the dielectric layer is arranged between the source electrode layer and the grid electrode structure, the source electrode layer is provided with a plurality of concave parts extending towards one side of the substrate, and the channel layer is partially filled in the concave parts and is electrically connected with the source electrode layer. In some alternative embodiments, a fill layer is also included, the fill layer being located between the channel layer and the drain layer and filling the recess. In some alternative embodiments, the recess has a profile shape that is one of an arcuate configuration or a U-shaped configuration. In some alternative embodiments, the filler layer includes a first portion and a second portion, the first portion being located above and in contact with the second portion, and the maximum width W2 of the second portion being less than the maximum width W1 of the first portion. In some alternative embodiments, the filler layer further comprises a third portion, the second portion being located between the first portion and the third portion, the maximum width W3 of the third portion being greater than the maximum width W2 of the second portion. In some alternative embodiments, the maximum width W3 of the third portion is less than the maximum width W1 of the first portion. In some alternative embodiments, the gate dielectric layer includes a first dielectric portion and a second dielectric portion connected to each other, the second dielectric portion being in direct contact with the channel layer. In some alternative embodiments, the second dielectric portion is in direct contact with the source layer. In some alternative embodiments, the second dielectric portion is located above the source layer with a portion of the dielectric layer between the second dielectric portion and the source layer. In some alternative embodiments, the gate dielectric layer has an L-shaped profile. In some alternative embodiments, a sacrificial layer between the gate dielectric layer and the channel layer is also included, the sacrificial layer having an L-shaped profile. In some alternative embodiments, the sidewalls of the first dielectric portion are in direct contact with the dielectric layer. The second aspect of the embodiment of the application also provides a preparation method of the semiconductor structure, which comprises the following steps: providing a substrate, and forming a source electrode layer on the substrate; Forming a dielectric layer on the source electrode layer, and forming a gate dielectric layer in the dielectric layer; forming a gate structure on a sidewall of the gate dielectric layer; Forming a recess extending towards one side of the substrate on the source electrode layer, and forming a channel layer so that the channel layer partially fills the recess, wherein the channel layer is electrically connected with the source electrode layer; a drain layer is formed on the channel layer. In some alternative embodiments, a method of formi