CN-118488334-B - Deep N-well driving type ramp buffer

Abstract

The present disclosure relates to a deep N-well driven ramp buffer. A local ramp buffer includes a deep N-well layer disposed in a P-substrate below a surface of the P-substrate, a P-well disposed between the surface of the P-substrate and the deep N-well layer, and an N-well structure disposed in the P-substrate and coupled to the deep N-well layer. The N-well structure is disposed between the surface of the P-substrate and the deep N-well layer. The P-well is disposed inside an opening in the N-well structure. The N-well structure and the deep N-well layer are configured to isolate the P-well within the opening. A source follower transistor is disposed in the P-well. The source follower transistor includes a gate terminal coupled to the N-well structure and a ramp generator.

Inventors

• CHEN SHAN
• EBIHARA HIROAKI
• WANG RUI
• TIAN ZHENFU

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260505

Application Date

20240131

Priority Date

20230210

Claims (18)

1. 1. A local ramp buffer, comprising: a deep N-well layer disposed in a P-substrate below a surface of the P-substrate; A P-well disposed between the surface of the P-substrate and the deep N-well layer; an N-well structure disposed in the P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the P-substrate and the deep N-well layer, wherein the P-well is disposed inside an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-well within the opening in the N-well structure between the surface of the P-substrate and the deep N-well layer, and A source follower transistor disposed in the P-well, wherein the source follower transistor includes a gate terminal coupled to the N-well structure and a ramp generator.
2. 2. The local ramp buffer of claim 1, wherein the source follower transistor further comprises: a first n+ doped region in the P-well proximate to the gate terminal to provide a drain terminal of the source follower transistor, wherein the drain terminal is coupled to a power line; a second N+ doped region in the P-well proximate to the gate terminal to provide a source terminal of the source follower transistor, and A p+ doped region in the P-well to provide a body terminal of the source follower transistor, wherein the source terminal is coupled to the body terminal and configured to provide an output node of the local ramp buffer.
3. 3. The local ramp buffer of claim 2, wherein a first diode is formed at a first interface between the N-well structure and the P-well, wherein an anode of the first diode is coupled to the body terminal and the source terminal, and wherein a cathode of the first diode is coupled to the gate terminal and the ramp generator.
4. 4. The local ramp buffer of claim 2, wherein a second diode is formed at a second interface between the N-well structure and the P-substrate, wherein an anode of the second diode is coupled to ground through the P-substrate, and wherein a cathode of the second diode is coupled to the gate terminal and the ramp generator.
5. 5. The local ramp buffer of claim 2, further comprising a current source coupled between the output node and ground.
6. 6. The local ramp buffer of claim 5, wherein the current source comprises: A first transistor, wherein a gate of the first transistor is coupled to receive a current source bias voltage, and A cascode transistor coupled to the first transistor, wherein a gate of the cascode transistor is coupled to receive a cascode bias voltage, and wherein the first transistor and the cascode transistor are coupled between the output node and ground.
7. 7. The local ramp buffer of claim 6, wherein the current source further comprises a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor, and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.
8. 8. The local ramp buffer of claim 1, wherein: The N-well structure includes a plurality of openings; the plurality of openings includes the opening; Each of the P-wells corresponding to a plurality of local ramp buffers is disposed within a respective one of the plurality of openings in the N-well structure, and The plurality of local ramp buffers includes the local ramp buffer.
9. 9. The local ramp buffer of claim 8, wherein the N-well structure and the deep N-well layer are configured to isolate each of the P-wells within the respective one of the plurality of openings in the N-well structure.
10. 10. A method of making a plurality of local ramp buffers, comprising: disposing a deep N-well layer in a P-substrate below a surface of the P-substrate; Disposing an N-well structure having a plurality of openings in the P-substrate and between the surface of the P-substrate and the deep N-well layer; Coupling the N-well structure to the deep N-well layer; Disposing a plurality of P-wells inside the plurality of openings in the N-well structure, wherein the N-well structure and the deep N-well layer are configured to isolate each of the plurality of P-wells within the plurality of openings in the N-well structure between the surface of the P-substrate and the deep N-well layer, and wherein each of the plurality of P-wells corresponds to one of the plurality of local ramp buffers, and A plurality of source follower transistors are disposed in the plurality of P-wells, wherein each of the plurality of source follower transistors includes a gate terminal coupled to the N-well structure and a ramp generator.
11. 11. The method of claim 10, wherein each of the plurality of P-wells is disposed in a respective one of the plurality of openings in the N-well structure.
12. 12. The method of claim 10, wherein each of the plurality of source follower transistors is disposed in a respective one of the plurality of P-wells.
13. 13. The method of claim 10, wherein each of the plurality of source follower transistors further comprises: A first n+ doped region in one of the plurality of P-wells proximate to the gate terminal to provide a drain terminal of the source follower transistor, wherein the drain terminal is coupled to a power line; A second N+ doped region located in said one of said plurality of P-wells proximate to said gate terminal to provide a source terminal of said source follower transistor, and A p+ doped region located in the one of the plurality of P-wells to provide a body terminal of the source follower transistor, wherein the source terminal is coupled to the body terminal and configured to provide an output node of a respective local ramp buffer.
14. 14. The method of claim 13, wherein for each of the plurality of local ramp buffers: forming a first diode at a first interface between the N-well structure and the P-well of the respective local ramp buffer; coupling the anode of the first diode to the body terminal and the source terminal, and A cathode of the first diode is coupled to the gate terminal and the ramp generator.
15. 15. The method of claim 13, wherein a second diode is formed at a second interface between the N-well structure and the P-substrate, wherein an anode of the second diode is coupled to ground through the P-substrate, and wherein a cathode of the second diode is coupled to the gate terminals of the plurality of source follower transistors and the ramp generator.
16. 16. The method as recited in claim 13, further comprising: for each of the plurality of local ramp buffers A current source is coupled between the output node and ground.
17. 17. The method of claim 16, wherein the current source comprises: A first transistor, wherein a gate of the first transistor is coupled to receive a current source bias voltage, and A cascode transistor coupled to the first transistor, wherein a gate of the cascode transistor is coupled to receive a cascode bias voltage, and wherein the first transistor and the cascode transistor are coupled between the output node and ground.
18. 18. The method of claim 17, wherein the current source further comprises a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor, and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.

Description

Deep N-well driving type ramp buffer Technical Field The present disclosure relates generally to image sensors, and in particular, but not exclusively, to High Dynamic Range (HDR) Complementary Metal Oxide Semiconductor (CMOS) image sensors. Background Image sensors have become ubiquitous and are now widely used in digital cameras, cellular telephones, security cameras, and in medical, automotive, and other applications. With the integration of image sensors into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, etc. of the image sensor in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. Techniques for manufacturing image sensors continue to progress rapidly. For example, the demand for higher resolution and lower power consumption has prompted further miniaturization and integration of these devices. A typical image sensor operates in response to image light from an external scene being incident on the image sensor. An image sensor includes a pixel array having a photosensitive element (e.g., photodiode) that absorbs a portion of incident image light and generates image charge upon absorption of the image light. The image charge generated by the pixel light can be measured as an analog output image signal on the column bit line that varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit lines as an analog image signal and converted into a digital value to generate a digital image (e.g., image data) representing an external scene. The analog image signals on the bit lines are coupled to readout circuitry including an input stage with analog-to-digital conversion (ADC) circuitry to convert those analog image signals from the pixel array to digital image signals. Disclosure of Invention In one aspect, the present disclosure provides a local ramp buffer comprising a deep N-well layer disposed in a P-substrate below a surface of the P-substrate, a P-well disposed between the surface of the P-substrate and the deep N-well layer, an N-well structure disposed in the P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the P-substrate and the deep N-well layer, wherein the P-well is disposed inside an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-well within the opening in the N-well structure between the surface of the P-substrate and the deep N-well layer, and a source follower transistor disposed in the P-well, wherein the source follower transistor includes a gate-follower coupled to the ramp generator terminal. In another aspect, the present disclosure provides a method of fabricating a plurality of local ramp buffers comprising disposing a deep N-well layer in a P-substrate below a surface of the P-substrate, disposing an N-well structure having a plurality of openings in the P-substrate and between the surface of the P-substrate and the deep N-well layer, coupling the N-well structure to the deep N-well layer, disposing a plurality of P-wells inside the plurality of openings in the N-well structure, wherein the N-well structure and the deep N-well layer are configured to isolate each of the plurality of P-wells within the plurality of openings in the N-well structure between the surface of the P-substrate and the deep N-well layer, and wherein each of the plurality of P-wells corresponds to one of the plurality of local ramp buffers, and disposing a plurality of source-follower transistors in the plurality of P-wells, wherein the source-follower transistors comprise a plurality of source-follower terminals. In yet another aspect, the present disclosure provides a local ramp buffer comprising a deep N-well layer disposed in a P-substrate below a surface of the P-substrate, a P-well disposed between the surface of the P-substrate and the deep N-well layer, an N-well structure disposed in the P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the P-substrate and the deep N-well layer, wherein the P-well is disposed inside an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-well within the opening of the N-well structure between the surface of the P-substrate and the deep N-well layer, and a source follower transistor disposed in the P-well, wherein the source follower transistor includes the n+ transistor, wherein the source follower transistor includes the p+ transistor, the source follower transistor includes the source follower transistor, and the source follower transistor includes the source follower transistor. Drawings Non-limiting and