CN-118678250-B - Method and apparatus for efficient reading of super-merged arrays from higher resolution sensors

Abstract

The present disclosure relates to methods and apparatus for efficiently reading super merge arrays from higher resolution sensors. The pixel includes a photosensor configured to photo-generate charge in response to incident light. The floating diffusion region is configured to receive charge photo-generated by the photosensor. The transfer transistor is coupled between the floating diffusion region and the photosensor. The dual floating diffusion DFD transistor is coupled to a floating diffusion region. The combining node is coupled to the DFD transistor. A floating diffusion region interconnect grid is coupled to the merge node of the pixel and the merge node of the second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the merge node to the active diffusion region when activated to provide a merged readout during a readout operation on the pixel array, and the DFD transistor is configured to not couple the merge node to the floating diffusion region when deactivated to provide a full resolution readout.

Inventors

• MITTUR ARAVINDKUMAR
• K.W. JOHNSON
• EBIHARA HIROAKI
• K. King en

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260512

Application Date

20240314

Priority Date

20231221

Claims (20)

1. 1. A pixel, comprising: a photosensor configured to photo-generate charge in response to incident light; A floating diffusion region configured to receive the charge photo-generated by the photosensor; A transfer transistor coupled between the floating diffusion region and the photosensor; a dual floating diffusion DFD transistor coupled to the floating diffusion; A merge node coupled to the DFD transistor, and A floating diffusion region interconnect grid coupled to the merge node of the pixel and a merge node of a second pixel, wherein the pixel and the second pixel are included in a plurality of pixels of a pixel array, Wherein the DFD transistor is configured to couple the merge node to the floating diffusion region when activated during a readout operation on the pixel array to provide a merged readout of the pixel and the second pixel, Wherein the DFD transistor is configured to not couple the merge node to the floating diffusion region when deactivated during the readout operation on the pixel array to provide full resolution readout of the pixel and the second pixel.
2. 2. The pixel of claim 1, further comprising: a source follower transistor having a gate coupled to the floating diffusion region, and A row select transistor coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a voltage supply and a bit line.
3. 3. The pixel of claim 2, wherein the row select transistor is configured to be activated in response to one of a first row select signal and a second row select signal during the readout operation to provide the full resolution readout of the pixel when the DFD transistor is deactivated.
4. 4. The pixel of claim 2, wherein the row select transistor is configured to be activated in response to a second row select signal during the readout operation to provide the combined readout of the pixel and the second pixel when the DFD transistor is activated and a row select transistor of the second pixel is deactivated.
5. 5. The pixel of claim 2, wherein a row select transistor of the second pixel is configured to be activated in response to a second row select signal during the readout operation to provide the combined readout of the pixel and the second pixel when the DFD transistor is activated and the row select transistor of the pixel is deactivated.
6. 6. The pixel of claim 2, wherein the bit line is a first bit line of a plurality of bit lines, wherein the row select transistor is configured to be activated in response to a second row select signal during the read out operation to provide the combined read out of the pixel and the second pixel when the DFD transistor is activated, wherein a row select transistor of the second pixel is coupled to the first bit line, wherein the row select transistor of the second pixel is activated in response to the second row select signal, wherein a row select transistor of a third pixel is coupled to a second bit line of the plurality of bit lines, wherein the row select transistor of the third pixel is deactivated in response to a row select signal.
7. 7. The pixel of claim 1, wherein the plurality of pixels includes 100 pixels included in a 10x10 block of pixels in the pixel array, wherein the floating diffusion region interconnect grid is coupled to a respective merge node included in each of the plurality of pixels.
8. 8. The pixel of claim 1, further comprising a reset transistor coupled between a pixel voltage supply and the merge node.
9. 9. An imaging system, comprising: a pixel array comprising a plurality of pixels arranged in rows and columns and a floating diffusion region interconnect grid coupled to the plurality of pixels, wherein each of the pixels comprises: a photosensor configured to photo-generate charge in response to incident light; A floating diffusion region configured to receive the charge photo-generated by the photosensor; A transfer transistor coupled between the floating diffusion region and the photosensor; A dual floating diffusion DFD transistor coupled to the floating diffusion region, and A merge node coupled to the DFD transistor; control circuitry coupled to the pixel array to control operation of the pixel array, and Readout circuitry coupled to receive either a combined readout or a full resolution readout from the pixel array, Wherein the floating diffusion region interconnect grid is coupled to the merge node of each of the pixels, Wherein the DFD transistor of each of the pixels is configured to couple the merge node to the floating diffusion region to provide the merged readout of the pixel array when activated during a readout operation on the pixel array, and Wherein the DFD transistor of each of the pixels is configured to not couple the merge node to the floating diffusion region when deactivated during the readout operation of the pixel array to provide the full resolution readout of the pixel array.
10. 10. The imaging system of claim 9, further comprising functional logic coupled to the readout circuitry to store and process digital representations of image charge values from the pixel array.
11. 11. The imaging system of claim 9, wherein each of the pixels further comprises: a source follower transistor having a gate coupled to the floating diffusion region, and A row select transistor coupled to the source follower transistor, Wherein the source follower transistor and the row select transistor of each of the pixels are coupled between a voltage supply and one of a plurality of bit lines.
12. 12. The imaging system of claim 11, wherein the row select transistors of the pixels are configured to be activated in response to a first or second row select signal during the readout operation to provide the full resolution readout of the pixel array when the DFD transistors of each of the pixels are deactivated.
13. 13. The imaging system of claim 11, wherein a row select transistor of one of the pixels is configured to be activated in response to a second row select signal during the readout operation to provide the merged readout of the pixel array when the DFD transistor of each of the pixels is activated and the row select transistors of the remaining of the pixels are deactivated.
14. 14. The imaging system of claim 11, wherein the row select transistors of a second subset of the plurality of pixels are configured to be activated in response to a second row select signal during the readout operation to provide the merged readout of the pixel array when the DFD transistors of each of the pixels are activated and the row select transistors of a first subset of the plurality of pixels are deactivated.
15. 15. The imaging system of claim 11, wherein a row select transistor of a first one of the pixels is coupled to a first one of the plurality of bit lines, wherein the row select transistor of the first pixel is configured to be activated in response to a second row select signal during the readout operation to provide the merged readout of the pixel array when the DFD transistors of each of the pixels are activated, wherein a row select transistor of a second one of the pixels is coupled to the first bit line, wherein the row select transistor of the second pixel is activated in response to the second row select signal, wherein a row select transistor of a third one of the pixels is coupled to a second one of the plurality of bit lines, wherein the row select transistor of the third pixel is deactivated in response to a first row select signal.
16. 16. The imaging system of claim 9, wherein the plurality of pixels includes 100 pixels included in a 10x10 block of pixels in the pixel array.
17. 17. The imaging system of claim 9, wherein each of the pixels further comprises a reset transistor coupled between a pixel voltage supply and the merge node.
18. 18. The imaging system of claim 11, wherein: the plurality of pixels includes a first plurality of pixels, The pixel array further comprises a second plurality of pixels, The row select transistors of a subset of the first plurality of pixels are coupled to a first bit line of the plurality of bit lines and are configured to be activated in response to a first row select signal during the read out operation to provide a combined read out of each of the first plurality of pixels when the DFD transistors of the first plurality of pixels are activated, an The row select transistors of a subset of the second plurality of pixels are coupled to a second bit line of the plurality of bit lines and are configured to be activated in response to a second row select signal during the read out operation to provide a merged read out of the second plurality of pixels when the DFD transistors of each of the second plurality of pixels are activated.
19. 19. The imaging system of claim 18, wherein the readout circuitry is coupled to the first and second bit lines and configured to concurrently receive the combined readout of the first plurality of pixels and the combined readout of the second plurality of pixels in parallel.
20. 20. The imaging system of claim 18, wherein the row select transistors of the subset of the first plurality of pixels are configured to be activated during the readout operation to provide a merged readout of the first plurality of pixels when the row select transistors of the remainder of the first plurality of pixels are deactivated, and wherein the row select transistors of the subset of the second plurality of pixels are configured to be activated during the readout operation to provide a merged readout of the second plurality of pixels when the row select transistors of the remainder of the second plurality of pixels are deactivated.

Description

Method and apparatus for efficient reading of super-merged arrays from higher resolution sensors Cross reference to related applications The present application claims the benefit of U.S. provisional patent application No. 63/490,478 to 2023, 3, 15, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates generally to image sensors, and in particular, but not exclusively, to Complementary Metal Oxide Semiconductor (CMOS) image sensors with pixel binning. Background Image sensors have become ubiquitous and are now widely used in digital cameras, cellular telephones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. Typical image sensors operate in response to image light from an external scene being incident on the image sensor. An image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of incident image light and generate image charge upon absorption of the image light. The image charge generated by the pixel light can be measured as an analog output image signal on the column bit line that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the column bit lines and converted into a digital value to provide information representative of an external scene. Disclosure of Invention One aspect of the disclosure relates to a pixel comprising a photosensor configured to photo-generate charge in response to incident light, a floating diffusion region configured to receive the charge photo-generated by the photosensor, a transfer transistor coupled between the floating diffusion region and the photosensor, a dual floating diffusion region (DFD) transistor coupled to the floating diffusion region, a merge node coupled to the DFD transistor, and a floating diffusion region interconnection grid coupled to the merge node of the pixel and a merge node of a second pixel, wherein the pixel and the second pixel are included in a plurality of pixels of a pixel array, wherein the DFD transistor is configured to couple the merge node to the floating diffusion region when activated to provide a merged readout of the pixel and the second pixel during a readout operation of the pixel array, wherein the DFD transistor is configured to not couple the floating diffusion node to the full resolution merge node and the second pixel when deactivated during the readout operation of the pixel array. Another aspect of the disclosure relates to an imaging system comprising a pixel array comprising a plurality of pixels arranged in rows and columns and a floating diffusion region interconnect grid coupled to the plurality of pixels, wherein each of the pixels comprises a photosensor configured to photo-generate charge in response to incident light, a floating diffusion region configured to receive the charge photo-generated by the photosensor, a transfer transistor coupled between the floating diffusion region and the photosensor, a Dual Floating Diffusion (DFD) transistor coupled to the floating diffusion region, and a merge node coupled to the DFD transistor, control circuitry coupled to the pixel array to control operation of the pixel array, and readout circuitry coupled to receive a merge readout or full resolution readout from the pixel array, wherein the floating diffusion region interconnect grid is coupled to the merge node of each of the pixels, wherein the DFD transistor of each of the pixels is configured to deactivate the floating diffusion region during operation of the pixel array and provide a full resolution readout to the pixel array during the pixel-to-merge-readout operation of the pixel array. Drawings Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the following drawings, wherein like or similar reference numerals are used to refer to like or similar components throughout unless otherwise specified. Additional details of the present technology are described in appendix a. FIG. 1 illustrates one example of an imaging system including a pixel array in accordance with the teachings of the present technique. Fig. 2 illustrates one example of a schematic diagram of one of a plurality of pixel circuits included in a pixel array in accordance with the teachings of the present technique. Fig. 3A-3B illustrate an example merge scheme of a pixel array in which 10x10 blocks of pixels are merged at floating diffusion regions by respective floating diffusion region interconnect grids in