CN-118943006-B - Semiconductor power device with low on-resistance and preparation method thereof

CN118943006BCN 118943006 BCN118943006 BCN 118943006BCN-118943006-B

Abstract

The invention relates to a preparation method of a low on-resistance semiconductor power device, which comprises the steps of forming a groove on a semiconductor substrate by etching, depositing high-purity undoped silicon in the groove to form an intrinsic silicon epitaxial layer, depositing a germanium-silicon epitaxial layer on the intrinsic silicon epitaxial layer, controlling the temperature below 800 ℃, controlling the germanium content to be less than 20 percent and the boron concentration to be less than 1E18cm ‑3 , and adopting a low-pressure chemical vapor deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE) or Physical Vapor Deposition (PVD) method, wherein the total gas pressure in the LPCVD method is less than 200torr. The flow rate of silane and germane gas is controlled so that the proportion of germane gas in the total gas flow rate is less than 20%. The invention solves the technical problem that the substrate resistance is affected due to the outward expansion of the P-type semiconductor material in the traditional high-temperature epitaxy process.

Inventors

LI KE
YANG TONGTONG
Gou Xuexin
ZHANG WENXIN
CAO XUEWEN
YAN TIANCAI
YANG LIEYONG
CHEN WEIYU

Assignees

物元半导体技术(青岛)有限公司

Dates

Publication Date: 20260508
Application Date: 20240723

Claims (2)

1. The preparation method of the semiconductor power device with low on-resistance is characterized by comprising the following steps: etching a semiconductor substrate to form a groove; Depositing high purity undoped silicon within the trench to form an intrinsic silicon epitaxial layer, comprising: preheating treatment is carried out in the reaction chamber, so that the surface of the substrate reaches the deposition temperature; Introducing high purity silane (SiH 4 ) gas into the reaction chamber; the temperature in the reaction chamber is regulated to be below 800 ℃ so that the intrinsic epitaxial layer reaches a set thickness; Depositing a germanium-silicon epitaxial layer on the intrinsic silicon epitaxial layer, controlling the temperature below 800 ℃, controlling the germanium content of the germanium-silicon epitaxial layer to be less than 20%, and controlling the boron concentration to be less than 1E18 cm - , wherein the deposition method comprises any one of low-pressure chemical vapor deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE) and Physical Vapor Deposition (PVD); Wherein the total gas pressure in the Low Pressure Chemical Vapor Deposition (LPCVD) process is less than 200torr; The low pressure chemical vapor deposition method controls the germanium content of the germanium-silicon epitaxial layer to be less than 20 percent, and comprises the following steps: Introducing silane (SiH 4 ) gas and germane (GeH 4 ) gas into the reaction chamber, and controlling the flow rate of the silane gas; controlling the flow of germane gas to make the proportion of germane gas to the total gas flow less than 20%; regulating the temperature in the reaction chamber to be kept below 800 ℃; The low pressure chemical vapor deposition method for controlling boron concentration of germanium-silicon epitaxial layer to be less than 1E18 cm - comprises introducing borane (B 2 H 6 ) gas into the reaction chamber during the process of depositing germanium-silicon epitaxial layer; The flow rate of the borane gas was adjusted to maintain the boron concentration at less than 1E18 cm - .
2. A low on-resistance semiconductor power device, comprising; A semiconductor substrate; a high purity undoped intrinsic silicon epitaxial layer within the trench; A germanium-silicon epitaxial layer in the trench, the germanium-silicon epitaxial layer being deposited on the intrinsic silicon epitaxial layer; Wherein the high purity undoped intrinsic silicon epitaxial layer and the germanium-silicon epitaxial layer in the trench are prepared by the preparation method of the low on-resistance semiconductor power device in claim 1.

Description

Semiconductor power device with low on-resistance and preparation method thereof Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to a low-on-resistance semiconductor power device and a preparation method thereof. Background The development of semiconductor power devices has been advancing toward increasing breakdown voltage and decreasing on-resistance. Along with the proposal and development of the superjunction theory, the semiconductor power device has lower on-resistance under the same voltage withstand condition, and the traditional silicon limit is broken through greatly. Currently, the manufacturing process of the superjunction device mainly comprises a multiple epitaxy technology, a deep groove etching filling technology and a high-energy particle injection technology. The occurrence of deep groove etching filling technology solves the problem of uneven super junction structure formed in multiple epitaxial processes, and becomes the main process choice for manufacturing the current super junction device. However, there are problems associated with conventional one-time high temperature epitaxy processes when deep trench etch fill techniques are employed. During the epitaxy process, the high temperature causes the P-type semiconductor material to expand out into the silicon on both sides of the deep trench, thereby affecting the resistivity of the substrate. This phenomenon results in unstable device performance, limiting further improvement of superjunction devices. Disclosure of Invention Aiming at the defects existing in the related art, the invention provides a low on-resistance semiconductor power device and a preparation method thereof, and solves the technical problem that the substrate resistance is affected due to the outward expansion of a P-type semiconductor material in the traditional high-temperature epitaxy process. In one possible embodiment, a method for preparing a low on-resistance semiconductor power device is provided, and comprises the steps of forming a groove on a semiconductor substrate by etching, depositing high-purity undoped silicon in the groove to form an intrinsic silicon epitaxial layer, depositing a germanium-silicon epitaxial layer on the intrinsic silicon epitaxial layer, controlling the germanium content of the germanium-silicon epitaxial layer to be less than 20% and the boron concentration to be less than 1E18 cm -3, wherein the deposition method comprises any one of low-pressure chemical vapor deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE) and Physical Vapor Deposition (PVD), wherein the total gas pressure in the low-pressure chemical vapor deposition (LPCVD) method is less than 200torr, controlling the germanium content of the germanium-silicon epitaxial layer to be less than 20% by the low-pressure chemical vapor deposition method comprises introducing silane (SiH 4) gas and germane (GeH 4) gas into a reaction chamber, controlling the flow of the silane gas, controlling the flow of the germane gas to occupy the total gas flow, and keeping the total gas flow to be less than 20 ℃ and the temperature in the reaction chamber to be less than 800 ℃. In one possible embodiment, wherein the low pressure chemical vapor deposition method controls the boron concentration of the germanium-silicon epitaxial layer to be less than 1E18 cm -3 comprises introducing a borane (B 2H6) gas into the reaction chamber during deposition of the germanium-silicon epitaxial layer, and adjusting the flow rate of the borane gas to maintain the boron concentration to be less than 1E18 cm -3. In one possible embodiment, where high purity undoped silicon is deposited in the trenches to form an intrinsic silicon epitaxial layer, a pre-heat treatment is performed in the reaction chamber to bring the substrate surface to the deposition temperature, high purity silane (SiH 4) gas is introduced into the reaction chamber, and the temperature in the reaction chamber is adjusted to below 800 ℃ to bring the intrinsic epitaxial layer to a set thickness. In one possible embodiment, wherein the total gas pressure in a Low Pressure Chemical Vapor Deposition (LPCVD) process is less than 200torr. In one possible embodiment, the low pressure chemical vapor deposition process controls the germanium content of the germanium-silicon epitaxial layer to less than 20%. In one possible embodiment, a low on-resistance semiconductor power device is provided, comprising a semiconductor substrate, a trench etched on the semiconductor substrate, a high-purity undoped intrinsic silicon epitaxial layer in the trench, a germanium-silicon epitaxial layer in the trench deposited on the intrinsic silicon epitaxial layer, wherein the high-purity undoped intrinsic silicon epitaxial layer and the germanium-silicon epitaxial layer in the trench are prepared by a preparation method of the low o