CN-119255600-B - Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, which are applied to the technical field of semiconductors. In the present invention, a semiconductor device having a height difference in a vertical direction between a plurality of lower electrodes is formed by removing a part of the height of at least one of the plurality of lower electrodes on a substrate.

Inventors

• XU PEIYU

Assignees

• 福建省晋华集成电路有限公司

Dates

Publication Date

20260512

Application Date

20241021

Claims (19)

1. 1. A method of fabricating a semiconductor device, comprising: providing a substrate comprising a first region and a second region; Forming a stacked structure layer on the first region and the second region, wherein the stacked structure layer comprises a support stacked layer and a first mask layer which are stacked from bottom to top, and the support stacked layer comprises a first sacrificial layer, a first support layer, a second sacrificial layer and a second support layer which are sequentially stacked from bottom to top; forming a through hole in the first region, wherein the through hole penetrates through the stacked structure layer; forming a lower electrode on the inner surface of the through hole and transversely extending to cover the first mask layer of the second region; forming a second mask layer on the lower electrode of the first region and the second region; And removing the second mask layer, part of the lower electrode and part of the first mask layer on the second region, so that the top surfaces of the lower electrodes on the two side walls of at least one through hole adjacent to the second region are at different levels and are in physical contact with the second supporting layer, and the top surfaces of the lower electrodes on the two side walls of at least one through hole are higher than the bottom surface of the second supporting layer and are lower than the top surface of the second supporting layer.
2. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the lower electrode on the second region comprises: Forming a first photoresist layer with a first opening on the second mask layer, wherein the first opening exposes a part of the top surface of the second mask layer on the first region and the top surface of the second mask layer on the second region; and removing the second mask layer, part of the lower electrode and part of the first mask layer corresponding to the first opening by taking the first photoresist layer as a mask so as to expose the support stack layer on the second region and the lower electrode on the side wall of the through hole adjacent to the support stack layer.
3. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising, after removing the lower electrode over the second region: The first photoresist layer and the second mask layer below the first photoresist layer are removed to expose the lower electrode on the first region.
4. 4. The method of manufacturing a semiconductor device of claim 2, wherein the via adjacent the support stack layer on the second region has opposing first and second sidewalls, the lower electrode on the first sidewall being in direct contact with the stack layer on the first region, the lower electrode on the second sidewall being in direct contact with the support stack layer on the second region.
5. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a top surface of the lower electrode on the first sidewall is higher than a top surface of the lower electrode on the second sidewall.
6. 6. The method of manufacturing a semiconductor device according to claim 5, wherein after removing the second mask layer on the first region, further comprising: and removing the lower electrode on the support stack layer between the adjacent through holes and the first mask layer below the lower electrode.
7. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of removing the lower electrode on the support stack layer between adjacent ones of the through holes and the first mask layer thereunder, a partial height of the lower electrode on the second side wall of the through hole adjacent to the support stack layer on the second region is also removed simultaneously.
8. 8. The method of manufacturing a semiconductor device according to claim 6, wherein after removing the second mask layer on the first region, further comprising: forming a third mask layer on the first region and the second region; And forming a second photoresist layer with a second opening on the third mask layer on the first region, wherein the second opening exposes part of the top surface of the third mask layer in the first region.
9. 9. The method of manufacturing a semiconductor device according to claim 8, wherein after removing the second mask layer over the first region, further comprising: and removing the first support layer and the second support layer in the third mask layer and the support stack layer corresponding to the second opening by taking the second photoresist layer as a mask.
10. 10. The method of manufacturing a semiconductor device according to claim 9, wherein after removing the second mask layer on the first region, further comprising: And removing the second sacrificial layer and the first sacrificial layer in the support stack layer in the first region and the second region.
11. 11. The method of manufacturing a semiconductor device according to claim 1, further comprising, after removing the second mask layer, the lower electrode, and the first mask layer over the second region: a metal oxide layer is formed on the lower electrode and an upper electrode is formed on the metal oxide layer.
12. 12. A semiconductor device, comprising: a substrate including a first region and a second region; A support structure comprising a first support structure located in the first zone and a second support structure located in the second zone, the second support structure having a length greater than the first support structure; and a plurality of lower electrodes positioned on the first region of the substrate, wherein at least part of top surfaces of the lower electrodes contacted with the second supporting structure on the second region are lower than the top surfaces of the rest of the lower electrodes, and are higher than the bottom surfaces of the second supporting structure and lower than the top surfaces of the second supporting structure.
13. 13. The semiconductor device according to claim 12, further comprising: A metal oxide layer on the plurality of lower electrodes; and an upper electrode on the metal oxide layer.
14. 14. The semiconductor device of claim 12, wherein the lower electrode in contact with the second support structure on the second region has opposing first and second sidewalls, the second sidewall contacting the second support structure, a top surface of the lower electrode on the first sidewall being higher than a top surface of the lower electrode on the second sidewall.
15. 15. The semiconductor device of claim 12, wherein the lower electrode in contact with the second support structure on the second region is on the same side of all remaining lower electrodes.
16. 16. The semiconductor device according to claim 12, wherein the lower electrode comprises a cylindrical shape or a columnar shape.
17. 17. A semiconductor device, comprising: A substrate; a support structure on the substrate; a plurality of lower electrodes are positioned on the substrate, wherein at least part of the top surface of one lower electrode is lower than all the other lower electrodes and positioned on the same side of all the other lower electrodes, and the lower electrodes physically contact the supporting structure, and the top surface of one lower electrode is also higher than the bottom surface of the supporting structure and lower than the top surface of the supporting structure.
18. 18. The semiconductor device according to claim 17, further comprising: A metal oxide layer on the plurality of lower electrodes; and an upper electrode on the metal oxide layer.
19. 19. The semiconductor device of claim 17, wherein said one of said lower electrodes has opposite first and second sidewalls, said second sidewall being located on a side away from all of the remaining lower electrodes, a top surface of said one of said lower electrodes located on said first sidewall being higher than a top surface of said one of said lower electrodes located on said second sidewall.

Description

Semiconductor device and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a semiconductor memory device and a manufacturing method thereof. Background With the trend toward miniaturization of various electronic products, the design of dynamic random access memory (dynamic randomaccess memory, DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, the current trend is that it has gradually replaced a DRAM cell with a planar gate structure because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure. In general, DRAM cells having recessed gate structures include a transistor element and a charge storage element to receive voltage signals from bit lines and word lines. However, due to the limited process technology, there are a number of drawbacks to the existing DRAM cells with recessed gate structures, which further improve and effectively enhance the performance and reliability of the associated memory devices. Disclosure of Invention The invention aims to provide a preparation method of a semiconductor structure, which is used for improving the efficiency and reliability of a semiconductor device. In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, which at least includes: providing a substrate comprising a first region and a second region; Forming a stacked structure layer on the first region and the second region, wherein the stacked structure layer comprises a support stacked layer and a first mask layer which are stacked up from bottom to top; forming a through hole in the first region, wherein the through hole penetrates through the stacked structure layer; forming a lower electrode on the inner surface of the through hole and transversely extending to cover the first mask layer of the second region; forming a second mask layer on the lower electrode of the first region and the second region; and removing the second mask layer, part of the lower electrode and part of the first mask layer on the second region so that the top surfaces of the lower electrodes on two side walls of at least one through hole adjacent to the second region are at different levels. Optionally, the step of removing the lower electrode on the second region may include: Forming a first photoresist layer with a first opening on the second mask layer, wherein the first opening exposes a part of the top surface of the second mask layer on the first region and the top surface of the second mask layer on the second region; And removing the second mask layer, the part of the lower electrode and the part of the first mask layer corresponding to the first opening by taking the first photoresist layer as a mask so as to expose the support stack layer on the second region and the lower electrode on the side wall of the through hole adjacent to the support stack layer. Optionally, after removing the lower electrode on the second region, the method may further include: The first photoresist layer and the second mask layer below the first photoresist layer are removed to expose the lower electrode on the first region. Optionally, the via adjacent to the support stack layer on the second region has opposite first and second sidewalls, the lower electrode on the first sidewall being in direct contact with the stack layer on the first region, the lower electrode on the second sidewall being in direct contact with the support stack layer on the second region. Optionally, a top surface of the lower electrode on the first sidewall is higher than a top surface of the lower electrode on the second sidewall. Alternatively, the support stack layer may include a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer sequentially stacked from bottom to top. Optionally, after removing the second mask layer on the first region, the method further includes: and removing the lower electrode on the support stack layer between the adjacent through holes and the first mask layer below the lower electrode. Optionally, in the step of removing the lower electrode on the support stack layer and the first mask layer thereunder between adjacent the through holes, a partial height of the lower electrode on the second sidewall of the through hole adjacent to the support stack layer on the second region is also removed simultaneously. Optionally, after removing the second mask layer on the first region, the method further includes: forming a third mask layer on the first region and the second region; And forming a second photoresist layer with a second opening on the third mask layer on the first region, wherein the second opening exposes part of the top surface of the third mask layer in the first region. Optionally, after r