CN-119255604-B - Semiconductor device and method for manufacturing the same

CN119255604BCN 119255604 BCN119255604 BCN 119255604BCN-119255604-B

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The semiconductor device includes a substrate, a stacked structure, and a first capping layer. The stacked structure is disposed on a substrate and includes an array portion and a first step portion, wherein the first step portion has a plurality of first step surfaces with gradually decreasing heights along a first direction. The first cover layer is arranged on the stacking structure, covers the array part and exposes the first step part, wherein the top surface of the first cover layer is higher than the topmost surface of the first step part. The plurality of first step surfaces are simultaneously aligned with the sidewalls of the first cladding layer in a direction perpendicular to the substrate. Therefore, the length ratio or the area ratio of the first step part relative to the array part is effectively reduced, so that the structure of the semiconductor device is more compact and stable, and the optimal operation performance can be achieved.

Inventors

XU PEIYU
CAI JIANCHENG
Kong Guoguo
HE SHIWEI
WU JIANSHAN
JIANG LIZHEN
WU YUAN
HUANG SHIPING

Assignees

福建省晋华集成电路有限公司

Dates

Publication Date: 20260505
Application Date: 20241024

Claims (11)

1. A semiconductor device, comprising: A substrate; A stacked structure disposed on the substrate and including an array portion, a first step portion having a plurality of first step surfaces with gradually decreasing heights along a first direction, and a second step portion A first cover layer disposed on the stack structure, covering the array portion and exposing the first step portion, a top surface of the first cover layer being higher than a topmost surface of the first step portion; The plurality of first step surfaces are simultaneously aligned with the sidewalls of the first cladding layer in a direction perpendicular to the substrate; The second step part is provided with a plurality of second step surfaces with gradually increasing heights along the first direction, each second step surface and each first step surface are arranged in a staggered manner in a second direction, and the second direction is perpendicular to the first direction; the stacked structure comprises a plurality of groups of conductive-dielectric layer pairs which are sequentially arranged in the vertical direction, wherein one group of conductive-dielectric layer pairs are formed by the conductive layer and a dielectric layer above the conductive layer.
2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: A plurality of first plugs disposed on the first step portions and electrically connected to the conductive layers of a part of the conductive-dielectric layer pairs, respectively, and An isolation layer covering the first cover layer and the topmost surface of the first step portion.
3. The semiconductor device according to claim 2, wherein, An etching stop layer is provided on the substrate between the first step portion and the second step portion in the vertical direction; Further comprises: And a second cover layer disposed over the first cover layer, covering the top surface of the first cover layer, and the topmost surface and the plurality of sidewalls of the first stepped portion, and exposing the second stepped portion.
4. A method of fabricating a semiconductor device, comprising: Providing a substrate; forming a plurality of conductive layers and a plurality of dielectric layers which are alternately stacked on the substrate to form a plurality of groups of conductive-dielectric layer pairs, wherein one group of conductive-dielectric layer pairs are formed by the conductive-dielectric layer pairs together with the conductive layer and a dielectric layer above the conductive layer; forming a first capping layer over the pair of conductive-dielectric layers exposing a first region of the pair of conductive-dielectric layers and covering a second region of the pair of conductive-dielectric layers; Forming a second mask layer on the first cover layer, exposing the first region from a notch portion of the second mask layer; performing a first etch process through the second mask layer, partially removing one set of the conductive-dielectric layer pair; Repeating the trimming-etching process to form a stacked structure, the stacked structure including an array portion formed in the second region and a first step portion formed in the first region, the first step portion having a plurality of first step surfaces with gradually decreasing heights in a first direction, and The second mask layer is completely removed, and the plurality of first step surfaces are simultaneously aligned with the sidewalls of the first capping layer in a direction perpendicular to the substrate.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the trim-etch manufacturing process further comprises: Performing a trimming process on the second mask layer to enlarge the notch until the first cover layer and the conductive-dielectric layer pair are partially exposed, and And performing a second etching manufacturing process through the trimmed second mask layer, and partially removing one group of conductive-dielectric layer pairs again.
6. The method of manufacturing a semiconductor device according to claim 4, further comprising, before forming the second mask layer: forming an etch stop layer on the substrate, vertically on a portion of the pair of conductive-dielectric layers; forming a first mask layer on the first cover layer, exposing a third region from the first mask layer, the third region being entirely within the first region; Partially removing said portion of the pair of conductive-dielectric layers and said etch stop layer through said first mask layer, and The first mask layer is completely removed.
7. The method for manufacturing a semiconductor device according to claim 6, further comprising: partially removing one set of the partial conductive-dielectric layer pairs by the first etch fabrication process; Repeating the trimming-etching process to form a second step portion in the third region in the stacked structure; forming a plurality of first plugs on the first step portions, electrically connected to the conductive layers of the corresponding conductive-dielectric layer pairs, respectively, and And forming a plurality of second plugs on the second step portions, the second plugs being electrically connected to the conductive layers of the respective conductive-dielectric layer pairs of the portions, the first plugs being staggered with the second plugs in a second direction, the second direction being perpendicular to the first direction.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the second step portion has a plurality of second step surfaces whose heights gradually decrease in the first direction.
9. The method for manufacturing a semiconductor device according to claim 7, wherein the second step portion has a plurality of second step surfaces whose heights gradually increase in the first direction.
10. The method for manufacturing a semiconductor device according to claim 6, further comprising, after forming the first step portion: Forming a second cover layer on the first cover layer, covering the topmost surface and the side walls of the first step portion of the first region, and exposing the third region; Forming another mask layer on the second cover layer to expose the first region from the notch portion of the other mask layer, and And repeating another trimming-etching manufacturing process through the second covering layer and the other mask layer, wherein a second step part is formed in the third region in the stacked structure, the second step part is provided with a plurality of second step surfaces, each second step surface and each first step surface are arranged in a staggered manner in a second direction, and the second direction is perpendicular to the first direction.
11. The method for manufacturing a semiconductor device according to claim 10, further comprising: Forming a plurality of first plugs on the first step portion, penetrating the second cover layer respectively covering the first step portion and electrically connected to the conductive layers of the corresponding conductive-dielectric layer pair, and And forming a plurality of second plugs on the second step portions, the second plugs being electrically connected to the conductive layers of the respective conductive-dielectric layer pairs of the portions, the first plugs being staggered with the second plugs in the second direction.

Description

Semiconductor device and method for manufacturing the same Technical Field The present application relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same. Background In modern electronics, memory plays an indispensable and important role. The memory is used for storing data of a user and storing program codes executed by the CPU and information which is required to be temporarily stored in the operation process. The memory can be divided into volatile memory (volatile memory) and nonvolatile memory (non-volatile memory). Common volatile memories include dynamic random access memory (dynamic random access memory, DRAM) and static random access memory (static random access memory, SRAM), which data disappears after power is turned off and must be re-entered at the next power supply. The nonvolatile memory includes a Read Only Memory (ROM) and a flash memory (flash memory), and data stored therein is still present even if the power is turned off, so that valid data stored earlier can be directly read after the power is re-supplied. With the progress of semiconductor manufacturing processes, memories have been shifted from planar structures to three-dimensional (3D) stacking to achieve higher cell densities in unit wafer area, meeting the demands for higher storage capacities. Three-dimensional memories typically include a stair-step structure (STAIRCASE STRUCTURE) formed on one or more sides of the memory stack structure to fan out (fan-out) layers of word lines (word lines) to electrically connect with interconnect structures, such as word line contact plugs. However, as the number of levels of the memory stack structure increases, the related fabrication process and device structure must be further improved to maintain good device performance while simplifying the fabrication process. Disclosure of Invention The application aims to provide a semiconductor device, wherein a step part which is electrically connected to a plug is arranged on one side of an array part, so that the length ratio or the area ratio of the step part relative to the array part can be effectively reduced, the structure of the semiconductor device is more compact and stable, and more optimized operation performance can be achieved. The application aims to provide a manufacturing method of a semiconductor device, which is characterized in that a covering layer is formed in advance to limit a step part to one side of an array part, so that the manufacturing process of the step part can be effectively simplified, the length ratio or the area ratio of the step part relative to the array part can be reduced, the structure of the manufactured semiconductor device is more compact and stable, and more optimized operation performance can be achieved. A semiconductor device provided in an embodiment of the application includes a substrate, a stacked structure, and a first capping layer. The stacked structure is disposed on the substrate and includes an array portion and a first step portion, wherein the first step portion has a plurality of first step surfaces of gradually decreasing height along a first direction. The first cover layer is arranged on the stacking structure, covers the array part and exposes the first step part, wherein the bottom surface of the first cover layer is higher than the topmost surface of the first step part. The plurality of first step surfaces are simultaneously aligned with the sidewalls of the first cladding layer in a direction perpendicular to the substrate. The manufacturing method of the semiconductor device provided by the embodiment of the application comprises the following steps. Providing a substrate, forming a stacked structure on the substrate, wherein the stacked structure comprises an array part and a first step part, wherein the array part is arranged on one side of the first step part, and the first step part is provided with a plurality of first step surfaces with gradually decreasing heights along a first direction. And forming a first cover layer on the stacked structure, covering the array part and exposing the first step parts, wherein the bottom surface of the first cover layer is higher than each first step surface. Drawings The accompanying drawings provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments. Fig. 1 is a top view of a semiconductor device according to a first embodiment of the present application; Fig. 2 is a schematic perspective view of a semiconductor device according to a first embodiment of the present application; Fig. 3 is a