CN-119277764-B - Memory and manufacturing method thereof

Abstract

The present disclosure relates to the field of semiconductors, and provides a memory and a method of manufacturing the same. The memory comprises a memory array, a plurality of bit lines, a first interconnection structure, a second interconnection structure, a bonding interface and a peripheral circuit, wherein the memory array comprises a plurality of vertical transistors and a plurality of memory cells, the bit lines are positioned on one side of the vertical transistors far away from the memory cells, the first interconnection structure is positioned on one side of the bit lines far away from the memory array, the second interconnection structure is positioned on one side of the first interconnection structure far away from the bit lines, the bonding interface is positioned between the first interconnection structure and the second interconnection structure, and the peripheral circuit is positioned on one side of the second interconnection structure far away from the first interconnection structure. The bit line is correspondingly coupled with the peripheral circuit through the first interconnection structure, the bonding interface and the second interconnection structure. The first interconnection structure comprises a first interconnection layer, the first interconnection layer comprises a plurality of first bonding pads and a plurality of first leads, the plurality of first bonding pads are correspondingly coupled with the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, and the larger the extension length is, the larger the width is for the plurality of first leads.

Inventors

• XIAO DEYUAN
• JIANG YI
• SI SHUFANG
• YANG CHEN
• Feng Daohuan
• ZHOU YING
• TANG YANZHE

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20230628

Claims (15)

1. 1. A memory, comprising: The memory array comprises a plurality of vertical transistors arranged in an array manner and a plurality of memory cells coupled with the plurality of vertical transistors in a one-to-one correspondence manner, wherein an active area of each vertical transistor extends along a first direction, and a first end of each vertical transistor is coupled with a first end of one memory cell; A plurality of bit lines located at one side of the plurality of vertical transistors far from the plurality of memory cells, extending along a second direction perpendicular to the first direction, and respectively coupled with the second ends of the plurality of vertical transistors; a first interconnect structure located on a side of the plurality of bit lines remote from the memory array; a second interconnect structure located on a side of the first interconnect structure away from the plurality of bit lines; A bonding interface between the first interconnect structure and the second interconnect structure; Peripheral circuitry located on a side of the second interconnect structure remote from the first interconnect structure, wherein the plurality of bit lines are correspondingly coupled to the peripheral circuitry through the first interconnect structure, the bonding interface, and the second interconnect structure; Wherein the first interconnect structure comprises a plurality of interconnect layers including a first interconnect layer adjacent to the plurality of bit lines, the first interconnect layer comprising a plurality of first pads and a plurality of first leads, the plurality of first pads being correspondingly coupled to the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, the plurality of first pads being the same size, the plurality of first contact plugs being the same size, For the plurality of first leads, the greater the extension length, the greater the width.
2. 2. The memory of claim 1, wherein the memory is configured to store, in the memory, The resistances of the plurality of first leads are the same.
3. 3. The memory according to claim 1 or 2, wherein, The plurality of first contact plugs are staggered on two sides of a perpendicular bisector of the plurality of bit lines, the extending direction of the perpendicular bisector is perpendicular to the first direction and the second direction respectively, and the distances from the plurality of first contact plugs to the perpendicular bisector are equal; The first contact plug located at one side of the perpendicular bisector is coupled with the bit line of the odd sequence, and the first contact plug located at the other side of the perpendicular bisector is coupled with the bit line of the even sequence.
4. 4. The memory of claim 3, wherein, The first pads coupled with the first contact plugs located at the same side of the perpendicular bisector are also located at the same side of the perpendicular bisector and are staggered along the extending direction of the perpendicular bisector.
5. 5. The memory according to claim 1 or 2, wherein, The plurality of first contact plugs are sequentially arranged along the perpendicular bisectors of the plurality of bit lines, and the extending directions of the perpendicular bisectors are respectively perpendicular to the first direction and the second direction; the first pads on one side of the perpendicular bisector are coupled with the first contact plugs of the odd order, and the first pads on the other side of the perpendicular bisector are coupled with the first contact plugs of the even order.
6. 6. The memory of claim 5, wherein the memory is configured to store, in the memory, The first bonding pads positioned on the same side of the perpendicular bisector are staggered along the extending direction of the perpendicular bisector.
7. 7. The memory according to claim 1 or 2, wherein, The plurality of interconnect layers further includes a second interconnect layer remote from the plurality of bit lines, the second interconnect layer including a plurality of second pads evenly distributed, the plurality of second pads being correspondingly coupled to the plurality of bit lines through a plurality of second contact plugs and other interconnect layers other than the second interconnect layer.
8. 8. The memory of claim 7, wherein the memory is configured to store, in the memory, The plurality of interconnect layers further includes at least one intermediate interconnect layer between the first interconnect layer and the second interconnect layer, the intermediate interconnect layer including a plurality of intermediate pads and a plurality of intermediate leads, the plurality of intermediate pads being correspondingly coupled to the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers between the intermediate interconnect layer and the plurality of bit lines; The occupied area of the middle bonding pad is larger than that of the first bonding pad, and the occupied area of the second bonding pad is larger than that of the middle bonding pad.
9. 9. The memory according to claim 1 or 2, characterized in that the memory further comprises: A plurality of word lines extending along a third direction, respectively covering partial sidewalls of the active regions of the plurality of vertical transistors, wherein the third direction is perpendicular to the first direction, and the third direction intersects the second direction; a plurality of word line contact plugs located between the plurality of word lines and the first interconnect structure; Wherein the plurality of word lines are correspondingly coupled with the peripheral circuit through the plurality of word line contact plugs, the first interconnect structure, the bonding interface, and the second interconnect structure.
10. 10. The memory of claim 9, wherein the memory is configured to store, in the memory, The word line contact plugs are distributed at two opposite ends of the word lines, the word line contact plugs at one end of the word lines are coupled with the word lines in odd order, and the word line contact plugs at the other end of the word lines are coupled with the word lines in even order.
11. 11. A method of manufacturing a memory, comprising: Forming a first semiconductor structure, wherein the first semiconductor structure comprises a memory array, a plurality of bit lines and a first interconnection structure, the memory array comprises a plurality of vertical transistors arranged in an array manner and a plurality of memory cells correspondingly coupled with the plurality of vertical transistors one by one, an active area of each vertical transistor extends along a first direction, a first end of each vertical transistor is coupled with a first end of each memory cell, the plurality of bit lines are positioned on one side of the plurality of vertical transistors far away from the plurality of memory cells, the plurality of bit lines extend along a second direction perpendicular to the first direction and are correspondingly coupled with second ends of the plurality of vertical transistors respectively, and the first interconnection structure is positioned on one side of the plurality of bit lines far away from the memory array; Forming a second semiconductor structure, wherein the second semiconductor structure comprises a peripheral circuit and a second interconnection structure positioned on the peripheral circuit; The first semiconductor structure and the second semiconductor structure are bonded in a mode of forming a bonding interface between the first interconnection structure and the second interconnection structure, so that the plurality of bit lines are correspondingly coupled with the peripheral circuit through the first interconnection structure, the bonding interface and the second interconnection structure, wherein the first interconnection structure comprises a plurality of interconnection layers, the plurality of interconnection layers comprise a first interconnection layer close to the plurality of bit lines, the first interconnection layers comprise a plurality of first bonding pads and a plurality of first leads, the plurality of first bonding pads are correspondingly coupled with the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, the plurality of first bonding pads are the same in size, and the plurality of first contact plugs are the same in size, and the larger the extension length and the larger the width are for the plurality of first bonding pads.
12. 12. The method for manufacturing a memory according to claim 11, wherein, Forming the first semiconductor structure, including: etching a substrate from a first face to form a plurality of active regions arranged in an array and a trench structure defining the plurality of active regions, each of the active regions extending in a first direction perpendicular to the substrate; forming an isolation structure in the trench structure; Etching a portion of the isolation structure from the first side to form a plurality of word line trenches extending along a third direction, each of the word line trenches exposing a portion of a respective one of the active regions arranged along the third direction, the third direction being perpendicular to the first direction; Forming a gate dielectric layer and a word line in each word line groove in sequence; Doping the first end of each active region from the first face to form a first source drain region; forming the plurality of memory cells on the first side, wherein a first end of each memory cell is coupled with one of the first source drain regions; Thinning the substrate from the second side to expose a second end of each of the active regions; doping the second end of each active region from the second face to form a second source drain region; forming a plurality of bit lines extending along the second direction on the second face, the plurality of bit lines being respectively coupled with second source drain regions of the plurality of active regions, the second direction being perpendicular to the first direction and intersecting the third direction; a first interconnect structure is formed on the second side.
13. 13. The method of manufacturing a memory device according to claim 12, wherein, Forming a first interconnect structure on the second side, comprising: forming the first interconnection layer on the second face, wherein the first interconnection layer is positioned on the plurality of bit lines; And forming at least one intermediate interconnection layer on the first interconnection layer, wherein the intermediate interconnection layer comprises a plurality of intermediate bonding pads and a plurality of intermediate leads, and the plurality of intermediate bonding pads are correspondingly coupled with the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs and other interconnection layers positioned between the intermediate interconnection layer and the plurality of bit lines, wherein the occupied area of the intermediate bonding pads is larger than that of the first bonding pads.
14. 14. The method of manufacturing a memory device according to claim 13, wherein, Forming a first interconnect structure on the second side, further comprising: And forming a second interconnection layer on the intermediate interconnection layer, wherein the second interconnection layer comprises a plurality of uniformly distributed second bonding pads, the second bonding pads are correspondingly coupled with the bit lines through a plurality of second contact plugs and other interconnection layers except the second interconnection layer, and the occupied area of the second bonding pads is larger than that of the intermediate bonding pads.
15. 15. The method of manufacturing a memory device according to claim 12, wherein forming the first semiconductor structure further comprises: And forming a plurality of word line contact plugs, wherein the plurality of word line contact plugs are positioned between the plurality of word lines and the first interconnection structure, and the plurality of word lines are correspondingly coupled with the peripheral circuit through the plurality of word line contact plugs, the first interconnection structure, the bonding interface and the second interconnection structure.

Description

Memory and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor technology, and in particular, to a memory and a method for manufacturing the same. Background With the development of the semiconductor field, the memory density of the planar memory cell is approaching the upper limit. Currently, three-dimensional memory architectures can address density limitations in planar memory cells. In a three-dimensional memory architecture, the memory cell array and peripheral circuits are located on different wafers and bonded together in a face-to-face fashion. However, in the wafer in the memory cell array, the bit line contact plugs have a small size and have a layout limitation, which is disadvantageous for the coupling of the bit lines to the peripheral circuits. Disclosure of Invention Accordingly, embodiments of the present disclosure provide a memory and a method for manufacturing the same to solve or improve the technical problems in the background art. The embodiment of the disclosure provides a memory, which comprises a memory array, a plurality of memory cells and a plurality of memory cells, wherein the memory array comprises a plurality of vertical transistors arranged in an array manner and a plurality of memory cells coupled with the plurality of vertical transistors in a one-to-one correspondence manner, an active area of each vertical transistor extends along a first direction, and a first end of each vertical transistor is coupled with a first end of one memory cell; the memory device comprises a plurality of memory cells, a plurality of bit lines, a first interconnection structure, a second interconnection structure, a bonding interface, a peripheral circuit and a plurality of plugs, wherein the bit lines are located on one side, far away from the memory cells, of the plurality of vertical transistors, extend along a second direction perpendicular to the first direction, are correspondingly coupled with second ends of the plurality of vertical transistors, the first interconnection structure is located on one side, far away from the memory array, of the plurality of bit lines, the second interconnection structure is located on one side, far away from the plurality of bit lines, of the first interconnection structure, the bonding interface is located between the first interconnection structure and the second interconnection structure, the peripheral circuit is located on one side, far away from the first interconnection structure, of the second interconnection structure, the plurality of bit lines are correspondingly coupled with the peripheral circuit through the first interconnection structure, the bonding interface and the second interconnection structure, the first interconnection structure comprises a plurality of interconnection layers, the plurality of interconnection layers comprise a plurality of first bonding pads and a plurality of first leads, the first interconnection layers are located on one side, far away from the plurality of bit lines, the first interconnection layers comprise a plurality of first bonding pads and a plurality of first bonding pads are correspondingly connected with the plurality of bonding pads and the plurality of first bonding pads are correspondingly larger than the plurality of the first bonding pads and the plurality of bonding pads are larger than the plurality of the first bonding pads are correspondingly the plurality of bonding pads are larger than the plurality bonding pads and the plurality bonding pads are correspondingly the same. In some embodiments, the resistances of the plurality of first leads are substantially the same. In some embodiments, the plurality of first contact plugs are staggered on two sides of a perpendicular bisector of the plurality of bit lines, the extending directions of the perpendicular bisectors are perpendicular to the first direction and the second direction respectively, the distances from the plurality of first contact plugs to the perpendicular bisector are equal, the first contact plugs on one side of the perpendicular bisector are coupled with the odd bit lines, and the first contact plugs on the other side of the perpendicular bisector are coupled with the even bit lines. In some embodiments, the first pads coupled with the first contact plugs located at the same side of the perpendicular bisector are also located at the same side of the perpendicular bisector and staggered along the extending direction of the perpendicular bisector. In some embodiments, the plurality of first contact plugs are sequentially arranged along a perpendicular bisector of the plurality of bit lines, the extending directions of the perpendicular bisectors are perpendicular to the first direction and the second direction, the first pads on one side of the perpendicular bisector are coupled with the first contact plugs of odd order, and the first pads on the other side of the perpendicular