Search

CN-119377143-B - GPIO interface circuit and configuration method and configuration device thereof

CN119377143BCN 119377143 BCN119377143 BCN 119377143BCN-119377143-B

Abstract

The application discloses a GPIO interface circuit, a configuration method and a configuration device thereof, and belongs to the technical field of circuits. The GPIO interface circuit comprises a connecting pin, a detection module, a configuration state switching module and a configuration state switching module, wherein the input end of the detection module is connected with the connecting pin, the output end of the detection module is used for outputting the level at the connecting pin, the configuration state switching module is respectively connected with the connecting pin and the detection module and is used for switching the configuration state of the GPIO interface circuit until the level at the connecting pin is switched from a first level to a second level or from the first level to a third level, and the first level is a level higher than the second level and lower than the third level.

Inventors

  • LI FUGUI

Assignees

  • 维沃移动通信有限公司

Dates

Publication Date
20260508
Application Date
20241010

Claims (9)

  1. 1.A GPIO interface circuit comprising: a connection pin for connecting the control device with the controlled device; the input end of the detection module is connected with the connecting pin, and the output end of the detection module is used for outputting the level at the connecting pin; The configuration state switching module is respectively connected with the connecting pin and the detection module and is used for switching the configuration state of the GPIO interface circuit under the condition that the level at the connecting pin is a first level until the level at the connecting pin is switched from the first level to a second level or switched to a third level, and the first level is a level higher than the second level and lower than the third level; the configuration state of the GPIO interface circuit includes a first output state, a second output state, a first input state, a second input state, and a third input state, and the configuration state switching module includes: the output end of the output control module is connected with the connecting pin; the input end of the input control module is connected with the connecting pin; the configuration module comprises a first resistor and a second resistor, wherein the first end of the first resistor is used for being connected with a first power supply, the second end of the first resistor is connected with the connecting pin, the first end of the second resistor is connected with the connecting pin, and the second end of the second resistor is used for being grounded; The resistor control module is respectively connected with the first resistor and the second resistor; The output control module outputs the third level through the connecting pin in the first output state, outputs the second level through the connecting pin in the second output state, inputs signals through the connecting pin in the first input state, and controls the first resistor to cut in and the second resistor to cut out through the resistance control module, inputs signals through the connecting pin in the second input state, and controls the first resistor to cut out and the second resistor to cut in through the resistance control module, and controls the first resistor to cut out and the second resistor to cut out through the connecting pin in the third input state.
  2. 2. The GPIO interface circuit of claim 1, wherein the detection module comprises: A first comparison circuit, an input end of which is connected with the connection pin, the first comparison circuit outputting a high-level signal in a case where a level at the connection pin is lower than the third level, and outputting a low-level signal in a case where the level at the connection pin is equal to or higher than the third level; the input end of the second comparison circuit is connected with the connecting pin, the second comparison circuit outputs a low-level signal when the level at the connecting pin is lower than or equal to the second level, and the second comparison circuit outputs a high-level signal when the level at the connecting pin is higher than the second level; The first input end of the AND gate is connected with the output end of the first comparison circuit, and the second input end of the AND gate is connected with the output end of the second comparison circuit; wherein the level at the connection pin is the first level in the case where the output terminal of the first comparison circuit and the output terminal of the second comparison circuit simultaneously output the high-level signal.
  3. 3. The GPIO interface circuit of claim 2, wherein the first comparison circuit comprises: the first end of the third resistor is connected with the connecting pin; the first end of the fourth resistor is connected with the second end of the third resistor, and the second end of the fourth resistor is grounded; A first comparator, the negative phase input end of which is connected with the first end of the fourth resistor and the positive phase input end of which is used for inputting the voltage signal corresponding to the third level, and/or The second comparison circuit includes: A fifth resistor, wherein a first end of the fifth resistor is connected with the connecting pin; a first end of the sixth resistor is connected with a second end of the fifth resistor, and a second end of the sixth resistor is grounded; And the positive phase input end of the second comparator is connected with the first end of the sixth resistor, and the negative phase input end of the second comparator is used for inputting a voltage signal corresponding to the second level.
  4. 4. The GPIO interface circuit of claim 1, wherein the detection module comprises: and the input end of the analog-to-digital converter is connected with the connecting pin, and the output end of the analog-to-digital converter is used for outputting the level at the connecting pin.
  5. 5. The GPIO interface circuit of claim 4 wherein the analog-to-digital converter further has a power supply terminal, and wherein the detection module further comprises, in the event that the voltage input at the power supply terminal is less than the output voltage of the first power supply: a seventh resistor connected in series between the input end of the analog-to-digital converter and the connecting pin, wherein the first end of the seventh resistor is connected with the connecting pin; an eighth resistor, wherein a first end of the eighth resistor is connected with a second end of the seventh resistor, and a second end of the eighth resistor is grounded; the voltage division value of the output voltage of the first power supply at the eighth resistor is smaller than or equal to the voltage input by the power supply end.
  6. 6. A configuration method for a GPIO interface circuit according to any one of claims 1 to 5, wherein the configuration method comprises: acquiring the level at the connecting pin; Switching the configuration state of the GPIO interface circuit until the level at the connection pin is switched from the first level to the second level or to the third level under the condition that the level at the connection pin is the first level; Wherein the first level is a level higher than the second level and lower than the third level.
  7. 7. The configuration method according to claim 6, wherein, in the case that the level at the connection pin is the first level, switching the configuration state of the GPIO interface circuit until the level at the connection pin is switched from the first level to the second level or to the third level, specifically includes: Acquiring a first configuration state sequence under the condition that the level at the connecting pin is a first level, wherein the first configuration state sequence is a sequence determined according to a first output state, a second output state, a first input state, a second input state and a third input state; switching the configuration state of the GPIO interface circuit based on the first sequence of configuration states until the level at the connection pin switches from the first level to a second level or to a third level; The output control module outputs the third level through the connecting pin in the first output state, outputs the second level through the connecting pin in the second output state, inputs signals through the connecting pin in the first input state, and controls the first resistor to be cut in and the second resistor to be cut out through the resistance control module, inputs signals through the connecting pin in the second input state, and controls the first resistor to be cut out and the second resistor to be cut in through the resistance control module, and inputs signals through the connecting pin in the third input state, and controls the first resistor to be cut out and the second resistor to be cut out through the resistance control module.
  8. 8. A configuration device for a GPIO interface circuit according to any one of claims 1 to 5, wherein the configuration device comprises: The acquisition module is used for acquiring the level at the connecting pin; a switching module, configured to switch a configuration state of the GPIO interface circuit until the level at the connection pin is switched from the first level to the second level or to the third level, in a case where the level at the connection pin is the first level; Wherein the first level is a level higher than the second level and lower than the third level.
  9. 9. The configuration device according to claim 8, wherein the switching module is specifically configured to: Acquiring a first configuration state sequence under the condition that the level at the connecting pin is a first level, wherein the first configuration state sequence is a sequence determined according to a first output state, a second output state, a first input state, a second input state and a third input state; switching the configuration state of the GPIO interface circuit based on the first sequence of configuration states until the level at the connection pin switches from the first level to a second level or to a third level; The output control module outputs the third level through the connecting pin in the first output state, outputs the second level through the connecting pin in the second output state, inputs signals through the connecting pin in the first input state, and controls the first resistor to be cut in and the second resistor to be cut out through the resistance control module, inputs signals through the connecting pin in the second input state, and controls the first resistor to be cut out and the second resistor to be cut in through the resistance control module, and inputs signals through the connecting pin in the third input state, and controls the first resistor to be cut out and the second resistor to be cut out through the resistance control module.

Description

GPIO interface circuit and configuration method and configuration device thereof Technical Field The application belongs to the technical field of circuits, and particularly relates to a GPIO interface circuit, a configuration method and a configuration device thereof. Background General-purpose input/output (GPIO) is a General-purpose digital input/output port. In embedded systems, GPIOs are designed as flexible pins that can be configured as inputs or outputs to meet different application requirements. The control device and the controlled device can be connected through the GPIO interface circuit so as to realize control and information interaction between the devices. In order to realize accurate transmission of information, the connection pins in the GPIO interface circuit need to accurately output a high level or a low level, if the level output by the connection pins in the GPIO interface circuit is a level between the low level and the high level, the connection pins are determined to be in an uncertain state, namely a half-high level, and if the connection pins keep half-high level operation, the reliability of the equipment where the GPIO interface circuit is located is affected. Disclosure of Invention The embodiment of the application aims to provide a GPIO interface circuit, a configuration method and a configuration device thereof, which can solve the problem that the reliability of equipment where the GPIO interface circuit is located is affected if a connecting pin keeps half-high level operation. In a first aspect, an embodiment of the present application provides a GPIO interface circuit, including a connection pin, a detection module, an input end of the detection module being connected to the connection pin, an output end of the detection module being configured to output a level at the connection pin, and a configuration state switching module, the configuration state switching module being respectively connected to the connection pin and the detection module, and being configured to switch a configuration state of the GPIO interface circuit until the level at the connection pin is switched from a first level to a second level or to a third level, where the first level is a level higher than the second level and lower than the third level, where the level at the connection pin is the first level. In a second aspect, an embodiment of the present application provides a configuration method, for a GPIO interface circuit according to any one of the first aspect, where the configuration method includes obtaining a level at a connection pin, and switching a configuration state of the GPIO interface circuit until the level at the connection pin is switched from a first level to a second level or to a third level, where the first level is a level higher than the second level and lower than the third level, if the level at the connection pin is the first level. In a third aspect, an embodiment of the present application provides a configuration device, configured for a GPIO interface circuit according to any one of the first aspect, where the configuration device includes an acquisition module configured to acquire a level at a connection pin, and a switching module configured to switch a configuration state of the GPIO interface circuit until the level at the connection pin is switched from a first level to a second level or to a third level, where the first level is a level higher than the second level and lower than the third level, if the level at the connection pin is the first level. In a fourth aspect, embodiments of the present application provide an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, performs steps of a method as in the second aspect. In a fifth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of a method as in the second aspect. In a sixth aspect, embodiments of the present application provide a chip comprising a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to execute programs or instructions to implement a method as in the second aspect. In a seventh aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement a method as in the second aspect. In an embodiment of the present application, a GPIO interface circuit is provided, where the GPIO interface circuit includes a connection pin, a detection module, and a configuration state switching module. In the process, the detection module can be used for directly detecting whether the level at the connecting pin is the first level, namely detecting whether the level at the connecting