CN-119486112-B - Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device comprises a plurality of memory cells stacked along a vertical substrate direction, wherein the memory cells comprise transistors and capacitors, the transistors of the memory cells are distributed in different layers and stacked along the vertical substrate direction, word lines extending through the different layers and along the vertical substrate direction, the transistors comprise first electrodes, second electrodes and semiconductor layers surrounding the side walls of the word lines, the capacitors comprise first electrodes and second electrodes, the first electrodes are connected with the first electrodes, the first electrodes of the capacitors of the memory cells are distributed in the different layers and stacked along the vertical substrate direction, and the semiconductor device further comprises at least one first through hole penetrating through the first electrodes of the different layers and comprises a vertical portion extending in the vertical substrate direction. According to the scheme provided by the embodiment, the second pole of the capacitor is arranged in the hole of the first pole, so that the area of the device is reduced, the density of the device is increased, the process is simplified, and the cost is reduced.

Inventors

• GUI WENHUA
• AI XUEZHENG
• WANG SHAOHUA
• DUAN JINGJING
• WANG XIANGSHENG
• WANG GUILEI
• DAI JIN

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20230810

Claims (15)

1. 1. A semiconductor device, the semiconductor device comprising: The memory unit comprises transistors and capacitors connected with the transistors, wherein the transistors of the memory units are distributed in different layers and stacked along the vertical substrate direction; Word lines extending through the different layers along a direction perpendicular to the substrate; The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the side wall of the word line, wherein the capacitor comprises a first electrode and a second electrode, the first electrode is connected with the first electrode, and the first electrodes of the capacitors of the storage units are distributed in different layers and stacked along the vertical substrate direction; The semiconductor device further comprises at least one first through hole penetrating through the first poles of different layers, wherein the second poles comprise vertical parts which are arranged in the first through holes and extend along the direction perpendicular to the substrate, and surrounding parts which wrap the end faces of the first poles far away from the word lines and the side walls adjacent to the end faces and perpendicular to the substrate, wherein the first poles completely surround the vertical parts, and insulating layers are filled between the adjacent first poles along the direction perpendicular to the substrate.
2. 2. The semiconductor device according to claim 1, wherein the semiconductor device includes a plurality of the first through holes penetrating through the same first pole, and the plurality of the first through holes penetrating through the same first pole are arranged along an extending direction of the first pole.
3. 3. The semiconductor device of claim 1, wherein the first pole and the first electrode are connected to form a unitary structure.
4. 4. The semiconductor device according to claim 1, wherein a plurality of semiconductor layers of the plurality of transistors are arranged at intervals, and the plurality of semiconductor layers distributed in a direction perpendicular to a substrate are distributed in different regions of the word line side wall.
5. 5. The semiconductor device of claim 1, wherein the transistor further comprises a gate insulating layer disposed between the word line and the semiconductor layer around the word line sidewall; the semiconductor device further includes: The insulating layers and the conductive layers are alternately distributed in sequence from bottom to top along the direction vertical to the substrate; The second through holes penetrate through each insulating layer and each conducting layer, and the word lines, the gate insulating layers surrounding the side walls of the word lines and the semiconductor layers surrounding different areas of the side walls of the gate insulating layers are sequentially distributed in the second through holes from inside to outside; The semiconductor layers extend along the direction vertical to the substrate and are disconnected at the side wall of the insulating layer, and the conductive layer comprises the first electrode and the second electrode.
6. 6. The semiconductor device according to claim 5, wherein a caliber of the second through hole corresponding to the first region of the conductive layer is larger than a caliber of the second region corresponding to the insulating layer; the conducting layer exposes the side wall in the second through hole, and the insulating layer exposes the side wall and partial areas of the upper surface and the lower surface in the second through hole; The semiconductor layer is distributed on the side wall of the conductive layer, and is distributed in partial areas of the upper surface and the lower surface of the insulating layer exposed in the second through hole and is not distributed on the side wall of the insulating layer.
7. 7. The semiconductor device according to claim 6, wherein the gate insulating layers are distributed on a surface of each of the semiconductor layers and are not distributed on a side wall of the insulating layer, and the gate insulating layers on the surfaces of the semiconductor layers of different layers are spaced apart from each other.
8. 8. The semiconductor device of claim 7, wherein the word line includes a second portion extending along the second via and a first portion located at a sidewall of each of the gate insulating layers.
9. 9. The semiconductor device according to claim 6, wherein a contact region of the conductive layer and the insulating layer is laterally etched to form a recessed region along a lateral direction, the recessed region being provided with an isolation layer distributed over a surface of the semiconductor layer and a surface of the gate insulating layer.
10. 10. A manufacturing method of a semiconductor device is characterized in that the semiconductor device comprises a plurality of memory cells stacked along a vertical substrate direction and word lines extending along the vertical substrate direction and penetrating through different layers, the memory cells comprise transistors and capacitors connected with the transistors, the transistors of the memory cells are distributed in the different layers and stacked along the vertical substrate direction, the transistors comprise a first electrode and a second electrode, and the manufacturing method of the semiconductor device comprises the following steps: Providing a substrate, wherein the substrate comprises an active area and a capacitance area at least arranged on one side of the active area, and sequentially and alternately depositing a first insulating film and a first conductive film on the active area and the capacitance area of the substrate to form a plurality of stacked structures, and each stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers; Etching the plurality of stacked structures, and simultaneously forming a groove penetrating the plurality of stacked structures, a plurality of first through holes and a plurality of second through holes, wherein the groove enables the first insulating layer and the conducting layer to form a preset pattern, the preset pattern of the conducting layer comprises a first electrode and a second electrode of the transistor to be formed, and a first pole of the capacitor is connected with the first electrode; Depositing a second insulating film filling the trench, the plurality of first through holes and the plurality of second through holes to form a second insulating layer, wherein the second insulating film is different from the first insulating film; etching to remove the second insulating layer in the groove of the capacitor region to expose the side wall of the first electrode, and etching to remove the second insulating layer in the first through holes; sequentially depositing a dielectric film and a second conductive film on the substrate, etching to remove the dielectric film and the second conductive film which are positioned in the active area, forming a dielectric layer and a second pole of the capacitor which are positioned in the capacitor area, wherein the second pole fills the first through hole and the groove which is positioned in the capacitor area, and the dielectric layer is arranged between the second pole and the first pole; and etching to remove the second insulating layer positioned in the second through hole, forming the word line extending along the direction vertical to the substrate in the second through hole, and forming a plurality of semiconductor layers surrounding the side wall of the word line of the transistors.
11. 11. The method for manufacturing the semiconductor device according to claim 10, wherein the word line extending in the vertical substrate direction is formed in the second via hole, and wherein a plurality of semiconductor layers of the plurality of transistors surrounding the word line side wall include: Transversely etching the conductive layer through wet etching, so that on a plane parallel to the substrate, the orthographic projection of the second through hole positioned on the first insulating layer falls into the orthographic projection of the second through hole positioned on the conductive layer, and the second through hole enables the first electrode and the second electrode in the preset pattern to be disconnected; Depositing a semiconductor film and a gate insulating film in the second through hole in sequence to form a plurality of layers of semiconductor layers and gate insulating layers of the transistor, wherein the semiconductor layers are connected with the first electrode and the second electrode; depositing a third conductive film in the second through hole to form a sacrificial layer, wherein the sacrificial layer covers the gate insulating layer; etching a part of the sacrificial layer in the second through hole, so that the side wall of the second through hole positioned on the first insulating layer exposes the gate insulating layer, and the side wall of the second through hole positioned on the conductive layer exposes the sacrificial layer; etching to remove the semiconductor layer and the gate insulating layer in the second through hole of the first insulating layer; and depositing a gate electrode film in the second through hole, wherein the gate electrode film fills the second through hole to form the word line.
12. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the etching the part of the sacrificial layer in the second via hole so that the gate insulating layer is exposed at a sidewall of the second via hole located in the insulating layer, and wherein the exposing the sacrificial layer at a sidewall of the second via hole located in the conductive layer comprises: Etching the sacrificial layer in the second through hole by a wet method so that the side wall of the second through hole positioned on the insulating layer exposes the gate insulating layer; And removing the semiconductor layer and the gate insulating layer in the second through hole of the insulating layer by wet etching.
13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein after the etching removes the semiconductor layer and the gate insulating layer located in the second via hole of the insulating layer, before depositing a gate electrode film in the second via hole, further comprising: depositing a third insulating film in the second through hole to form an isolation layer; and etching to remove the isolation layer covered on the sacrificial layer.
14. 14. The method for manufacturing the semiconductor device according to claim 11, wherein after forming the word line extending in the vertical substrate direction in the second via hole, and a plurality of semiconductor layers surrounding the word line side wall of the plurality of transistors, further comprising: And etching the second insulating layer in the groove of the active area, depositing a third insulating film filling the groove of the active area, and forming a third insulating layer.
15. 15. An electronic apparatus comprising the semiconductor device according to any one of claims 1 to 9, or comprising the semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 10 to 14.

Description

Semiconductor device, manufacturing method thereof and electronic equipment Technical Field Embodiments of the present disclosure relate to device design and fabrication thereof, and more particularly to a semiconductor device, a fabrication method thereof, and an electronic device. Background Semiconductor memory is divided into volatile memory (RAM, including DRAM, SRAM, etc.) and nonvolatile memory (ROM and non-ROM) from an application perspective. Taking DRAM as an example, conventionally known DRAMs have multiple repeated "memory cells," each having a capacitor and transistor. The capacitor can store 1bit of data, and after charging and discharging, the quantity of the stored charges of the capacitor can respectively correspond to binary data of '1' and '0'. The transistor is a switch for controlling the charge and discharge of the capacitor. In order to reduce the cost of the product as much as possible, it is desirable to make as many memory cells as possible on a limited substrate. Since moore's law emerged, various semiconductor structural designs and process optimizations have been proposed in the industry to meet the needs of people for current products. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The embodiment of the disclosure provides a semiconductor device, a manufacturing method thereof and electronic equipment, and the semiconductor device simplifies the process and reduces the cost. Embodiments of the present disclosure provide a semiconductor device including: The memory unit comprises transistors and capacitors connected with the transistors, wherein the transistors of the memory units are distributed in different layers and stacked along the vertical substrate direction; Word lines extending through the different layers along a direction perpendicular to the substrate; The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the side wall of the word line, wherein the capacitor comprises a first electrode and a second electrode, the first electrode is connected with the first electrode, and the first electrodes of the capacitors of the storage units are distributed in different layers and stacked along the vertical substrate direction; The semiconductor device further includes at least one first via penetrating the first pole of the different layers, and the second pole includes a vertical portion disposed within the first via extending in a direction perpendicular to the substrate. In some embodiments, the semiconductor device includes a plurality of the first through holes, and the plurality of first through holes are arranged along an extending direction of the first pole. In some embodiments, the second pole further includes a wrap-around portion wrapping an end face of the first pole remote from the word line and a sidewall perpendicular to a substrate direction adjacent to the end face. In some embodiments, the first pole and the first electrode are connected to form a unitary structure. In some embodiments, the plurality of semiconductor layers of the plurality of transistors are spaced apart, the plurality of semiconductor layers being distributed over different regions of the wordline sidewall. In some embodiments, the transistor further includes a gate insulating layer disposed between the word line and the semiconductor layer surrounding the word line sidewall; the semiconductor device further includes: The insulating layers and the conductive layers are alternately distributed in sequence from bottom to top along the direction vertical to the substrate; The second through holes penetrate through each insulating layer and each conducting layer, and the word lines, the gate insulating layers surrounding the side walls of the word lines and the semiconductor layers surrounding different areas of the side walls of the gate insulating layers are sequentially distributed in the second through holes from inside to outside; The semiconductor layers extend along the direction vertical to the substrate and are disconnected at the side wall of the insulating layer, and the conductive layer comprises the first electrode and the second electrode. In some embodiments, the second via has a larger caliber for a first region of the conductive layer than for a second region of the insulating layer; the conducting layer exposes the side wall in the second through hole, and the insulating layer exposes the side wall and partial areas of the upper surface and the lower surface in the second through hole; The semiconductor layer is distributed on the side wall of the conductive layer, and is distributed in partial areas of the upper surface and the lower surface of the insulating layer exposed in the second through hole and is not distributed on the side wall of the insulating layer. In some embodiments, the gate insulating layers are