CN-119537293-B - High-speed communication method, system, device and storable medium between dual-core processors

CN119537293BCN 119537293 BCN119537293 BCN 119537293BCN-119537293-B

Abstract

The invention discloses a high-speed communication method, a system, equipment and a storage medium between dual-core processors, wherein the method comprises the steps of distributing a shared area in a memory, establishing a communication channel, dividing a piece of memory managed by each processor into memory blocks with fixed sizes, forming a memory pool by memory block pointers, acquiring the memory block pointers from the memory pool, managing pointers by adopting a ring buffer structure, acquiring the memory block pointers pointed by write pointers from the ring buffer managed by a data reading end by the data writing end, writing data into the pointed memory blocks, acquiring and using the memory block pointers according to a read pointer by the data reading end, replacing the read memory block pointers by the new memory block pointers from the memory pool, and returning the used memory block pointers to the memory pool by the data reading end. The method uses the memory block pointer as a communication medium to avoid direct data copying, improves the data transmission efficiency, reduces the delay, and is suitable for application scenes with high real-time performance.

Inventors

WANG XIJUN
WEN HAORAN
CHEN XIANG
QIU JIYUN
Nong Panpan

Assignees

中山大学

Dates

Publication Date: 20260508
Application Date: 20241126

Claims (7)

1. The high-speed communication method between the dual-core processors is applied to the dual-core processors, and the dual-core processors are respectively connected with the internal memories, and is characterized by comprising the following steps of: S1, distributing a shared area in a memory to establish a communication channel, wherein the shared area is divided into four parts, including a channel information area, a ring buffer area structure area, a memory block area and an idle area, wherein the channel information area stores a channel name, a processor 0 ring buffer area base address, a processor 1 ring buffer area base address, a buffer area unit number N, a memory block size and a processor 0 memory block area base address, the processor 1 memory block area base address is used for storing two ring buffers managed by the processor, the memory block area is used for being cut by the processor to form a memory pool, the idle area represents unused residual memory, and the memory of the idle area can be distributed according to actual demands; S2, dividing a piece of memory managed by each dual-core processor into memory blocks with fixed sizes, and forming a memory pool by memory block pointers, wherein the process is as follows: S2.1, the processor obtains the size of the memory block from the channel information area, and the memory block is obtained by cutting the memory block area according to the preset size of the memory pool; s2.2, after segmentation, storing pointers pointing to the memory blocks into a pointer queue to form a memory pool; S3, acquiring a memory block pointer from the memory pool, and managing the memory block pointer by adopting a ring buffer area structure; S4, the data writing end acquires a memory block pointer pointed by the writing pointer from a ring buffer area managed by the data reading end, and writes the data into a memory block pointed by the memory block pointer; s5, the data reading end obtains and uses the memory block pointer according to the read pointer; S6, the data reading end acquires a new memory block pointer from the memory pool to replace the read memory block pointer, and the process of the step S6 is as follows: s6.1, after the data reading end takes out the memory block pointer, acquiring a new memory block pointer from a local memory pool of the data reading end to replace the memory block pointer; S6.2, the read pointer moves backwards by one position after the replacement operation is finished, and if the read pointer reaches the end position of the annular buffer area, the read pointer points to the initial position of the annular buffer area again; S7, the data reading end returns the used memory block pointer to the memory pool again.
2. The method of claim 1, wherein the ring buffer structure comprises a buffer header and N buffer units, The buffer table head contains information such as buffer write pointer, read pointer, buffer unit number and the like, The buffer unit contains a memory block pointer and a stored data length, The processor extracts an equivalent memory block pointer from the memory pool to fill the buffer unit according to the number N of the buffer units for initializing the ring buffer.
3. The high-speed communication method according to claim 2, wherein the step S4 process is as follows: S4.1, the data writing end obtains the base address of the annular buffer area of the data reading end from the channel information area, and finds the buffer area table head through the base address of the annular buffer area to obtain a writing pointer; S4.2, the data writing end copies the data to be written into the memory block after obtaining the memory block pointer according to the buffer area unit pointed by the writing pointer, and sets the length of the stored data in the buffer area unit as the data length; and S4.3, the write pointer moves backwards by one position after the write operation is finished, and if the end position of the annular buffer area is reached, the write pointer points to the initial position of the annular buffer area again.
4. A high-speed communication method according to claim 3, wherein the step S5 procedure is as follows: s5.1, the data reading end obtains a local annular buffer area base address from the channel information area, and finds a buffer area table head through the annular buffer area base address to obtain a read pointer; S5.2, the data reading end takes out the memory block pointer and the stored data length according to the buffer area unit pointed by the read pointer, and reads corresponding data at the memory block according to the stored data length.
5. A high-speed communication system between dual-core processors for performing the high-speed communication method of any one of claims 1 to 4, the high-speed communication system comprising: the communication channel establishing module is used for distributing the shared area in the memory and establishing a communication channel; The memory segmentation module is used for segmenting a piece of memory managed by each dual-core processor into memory blocks with fixed sizes, and forming a memory pool by memory block pointers; the memory block pointer management module is used for acquiring a memory block pointer from the memory pool and managing the memory block pointer by adopting a ring buffer area structure; The data writing module is used for acquiring a memory block pointer pointed by the writing pointer from the annular buffer area managed by the data reading end by the data writing end and writing the data into a memory block pointed by the memory block pointer; The first data reading module is used for the data reading end to acquire and use the memory block pointer according to the read pointer; The second data reading module is used for acquiring a new memory block pointer from the memory pool by the data reading end so as to replace the read memory block pointer; and the third data reading module is used for returning the used memory block pointer to the memory pool again by the data reading end.
6. A computer device comprising a processor and a memory for storing a program executable by the processor, wherein the processor, when executing the program stored in the memory, implements the high speed communication method of any one of claims 1 to 4.
7. A storage medium storing a program which, when executed by a processor, implements the high-speed communication method of any one of claims 1 to 4.

Description

High-speed communication method, system, device and storable medium between dual-core processors Technical Field The invention belongs to the technical field of dual-core communication, and particularly relates to a high-speed communication method, a high-speed communication system, computer equipment and a storable medium between dual-core processors. Background With the rapid development of computer communication technology, the data transmission requirement between processors is continuously increasing, and especially in a multi-core processor system, the communication efficiency between each processor directly influences the overall performance and instantaneity of the system. However, the existing inter-processor communication method mainly relies on data copy transmission by using a buffer, and has obvious defects in the scene of processing large data volume or having high requirements on real-time performance. Frequent data copying operations greatly reduce communication efficiency and introduce additional delays. With the increase of the data volume, the communication overhead of the system is obviously increased, and the overall processing speed is affected. Accordingly, the prior art still has problems to be solved in terms of high-speed, low-latency communication between processors. A new way of inter-processor communication is needed to solve this problem. Disclosure of Invention The main object of the present invention is to overcome the drawbacks and disadvantages of the prior art and to provide a method, system, computer device and storable medium for high-speed communication between dual-core processors. In order to achieve the above purpose, the present invention adopts the following technical scheme: In a first aspect, the present invention provides a high-speed communication method between dual-core processors, applied to dual-core processors, where the dual-core processors are respectively connected with a memory, the high-speed communication method includes the following steps: s1, distributing a shared area in a memory, and establishing a communication channel; s2, dividing a piece of memory managed by each dual-core processor into memory blocks with fixed sizes, and forming a memory pool by memory block pointers; S3, acquiring a memory block pointer from the memory pool, and managing the memory block pointer by adopting a ring buffer area structure; S4, the data writing end acquires a memory block pointer pointed by the writing pointer from a ring buffer area managed by the data reading end, and writes the data into a memory block pointed by the memory block pointer; s5, the data reading end obtains and uses the memory block pointer according to the read pointer; s6, the data reading end acquires a new memory block pointer from the memory pool to replace the read memory block pointer; s7, the data reading end returns the used memory block pointer to the memory pool again. Further, the step S1 specifically includes: A slice of region is divided in the memory as a shared region of the dual-core processor. The size of the shared area is determined by the actual requirements, which allows two processors to access at the same time. The shared area is divided into four parts including a channel information area, a ring buffer area structure area, a memory block area and an idle area. The channel information area stores the channel name, the base address of the annular buffer area of the processor 0, the base address of the annular buffer area of the processor 1, the number N of buffer area units, the size of the memory block, the base address of the memory block area of the processor 0 and the base address of the memory block area of the processor 1. The area is used for providing channel information for the processors and ensuring that the two processors acquire the consistency of the channel information, the annular buffer area structure area is used for storing annular buffer areas managed by the two processors, the memory block area is used for being segmented by the processors to form a memory pool, the idle area represents unused residual memory, and the memory of the idle area can be allocated according to actual requirements. Further, in step S2, each processor segments the portion managed by each memory block region, which specifically includes the following steps: s2.1, two processors acquire the size of a memory block from a channel information area, and divide the memory block from each managed part of the memory block area by taking the size of a memory pool defined in advance as the number to acquire the memory block; S2.2, each processor creates a queue for storing pointers, and each pointer pointing to the memory block is stored in the pointer queue to form a memory pool. Establishing a memory pool that allows the processor to obtain memory block pointers can facilitate the processor's management of memory blocks. Further, in the step S3, a memory block pointer is obtained f