CN-119556766-B - System for synchronizing high-speed clock based on low-speed clock, method, device and medium thereof

CN119556766BCN 119556766 BCN119556766 BCN 119556766BCN-119556766-B

Abstract

The invention provides a system for synchronizing a high-speed clock based on a low-speed clock, a method, a device and a medium thereof, wherein the system comprises an external clock source and a plurality of receiving devices, in the receiving devices, rising edge acquisition signals are output to a synchronous arbiter in response to rising edges of the external clock, and a cycle completion signal is output to the synchronous arbiter after the triggering edge count of the internal clock reaches a cycle count value, wherein the cycle count value is used for representing cycle times values of the internal clock and the external clock; and when the cycle completion signal and the rising edge acquisition signal are different, the cycle completion signal and the rising edge acquisition signal arrive at the synchronous arbiter, and clock synchronization is carried out on the later-stage processor through the synchronous processor. According to the technical scheme of the embodiment of the invention, the synchronization arbiter determines that the frequency offset occurs according to the fact that the cycle completion signal and the rising edge acquisition signal do not arrive at the same time, and triggers the synchronization processor to realize clock synchronization for the later-stage processor, so that the purpose that one external clock carries out plate-crossing synchronization on any number of receiving devices is achieved, and hardware complexity and cost are reduced.

Inventors

PANG XIANMING
ZHANG HUAZAN

Assignees

珠海芯业测控有限公司

Dates

Publication Date: 20260512
Application Date: 20241031

Claims (6)

1. A system for synchronizing a high-speed clock based on a low-speed clock, comprising: an external clock source for outputting an external clock; The receiving equipment comprises an external clock rising edge collector, an internal clock counter, a synchronous arbiter, an offset processing module, a synchronous processor and a post-processor, wherein the external clock rising edge collector is connected with the external clock source, the external clock rising edge collector and the internal clock counter are connected with the input end of the synchronous arbiter, the output end of the synchronous arbiter is connected with the input end of the offset processing module, the output end of the offset processing module is connected with the synchronous processor, and the synchronous processor is connected with the post-processor; The external clock rising edge collector responds to the rising edge of the external clock to output a rising edge collecting signal to the synchronous arbiter, the internal clock counter is used for counting the triggering edge of the internal clock, and after the counting value of the triggering edge reaches a preset period counting value, a period finishing signal is output, the period counting value is used for representing the multiple between the period of the external clock and the period of the internal clock, and the period of the external clock is larger than the period of the internal clock; the synchronous arbiter is used for triggering the offset processing module to send a synchronous trigger signal to the synchronous processor under the condition that the cycle completion signal and the rising edge acquisition signal do not arrive at the same time; wherein the synchronization processor adjusts a processing period of the post-processor to be the same as the external clock based on an offset between the internal clock and the external clock in response to the synchronization trigger signal; The offset processing module comprises a stopping processor, the output end of the stopping processor is connected with the input end of the synchronous processor, and the input end of the stopping processor is connected with the output end of the synchronous arbiter; when the rising edge collecting signal is later than the period completing signal and reaches the synchronous arbiter, the synchronous arbiter is used for triggering the stopping processor to output a pause enabling signal to the synchronous processor, the synchronous processor responds to the pause enabling signal, determines pause duration according to the arrival time difference of the period completing signal and the rising edge collecting signal, and controls the back-stage processor to pause operation based on the pause duration; when the external clock rising edge collector detects the next rising edge collecting signal, restarting the next processing period of the post-processor through the synchronous processor; The offset processing module further comprises an advanced processor, wherein the output end of the advanced processor is connected with the input end of the synchronous processor, and the input end of the advanced processor is respectively connected with the output end of the synchronous arbiter; And when the rising edge acquisition signal reaches the synchronous arbiter earlier than the period completion signal, the synchronous arbiter is used for triggering the advanced processor to output an advanced enabling signal to the synchronous processor, the synchronous processor responds to the advanced enabling signal, determines an advanced time length according to the arrival time difference, determines a target item of the current period based on the advanced time length, controls the later processor to process the target item in advance and starts the next processing period.
2. The system for synchronizing high-speed clocks based on a low-speed clock as recited in claim 1, wherein the external clock rising edge collector is connected to the internal clock counter, wherein the internal clock counter stops counting after outputting the cycle completion signal and restarts counting after clearing the count value of the trigger edge in response to the rising edge collection signal.
3. A method for synchronizing a high-speed clock based on a low-speed clock, which is applied to the system for synchronizing a high-speed clock based on a low-speed clock as claimed in any one of claims 1 to 2, the method comprising: The external clock source sends an external clock to each receiving device, and the rising edge collector detects the rising edge of the external clock and then sends a rising edge collecting signal to the synchronous arbiter; Counting the trigger edges of an internal clock through an internal clock counter, and sending a period completion signal to the synchronous arbiter when the count value of the trigger edges reaches a preset period count value, wherein the period count value is used for representing the multiple between the period of the external clock and the period of the internal clock, and the period of the external clock is larger than the period of the internal clock; when the rising edge acquisition signal and the period completion signal do not arrive at the same time, the synchronous arbiter triggers an offset processing module to send a synchronous trigger signal to a synchronous processor, and the synchronous processor adjusts the processing period of a later-stage processor to be the same as the external clock based on the offset between the internal clock and the external clock; The offset processing module comprises a stopping processor and an advance processor, wherein the output end of the stopping processor and the output end of the advance processor are respectively connected with the input end of the synchronous processor, and the input end of the stopping processor and the input end of the advance processor are respectively connected with the output end of the synchronous arbiter; the synchronization arbiter triggers an offset processing module to send a synchronization trigger signal to a synchronization processor, and the synchronization processor adjusts a processing period of a subsequent processor to be the same as the external clock based on an offset between the internal clock and the external clock, including: when the rising edge acquisition signal reaches the synchronous arbiter later than the cycle completion signal, the synchronous arbiter triggers the stop processor to output a pause enabling signal to the synchronous processor; The synchronous processor responds to the pause enabling signal, determines pause duration according to the arrival time difference of the period completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration; when the external clock rising edge collector detects the next rising edge collecting signal, restarting the next processing period of the subsequent processor through the synchronous processor; the synchronization arbiter triggers an offset processing module to send a synchronization trigger signal to a synchronization processor, and the synchronization processor adjusts a processing period of a subsequent processor to be the same as the external clock based on an offset between the internal clock and the external clock, including: When the rising edge acquisition signal reaches the synchronous arbiter earlier than the cycle completion signal, the synchronous arbiter triggers the advanced processor to output an advanced enable signal to the synchronous processor; The synchronization processor responds to the advance enabling signal and determines an advance duration according to the arrival time difference; And determining a target item of the current period based on the advanced time length, and controlling the post-processor to process the target item in advance and start the next processing period.
4. A method of synchronizing a high-speed clock based on a low-speed clock as recited in claim 3, wherein the external clock rising edge collector is coupled to the internal clock counter, the method further comprising, after sending a cycle complete signal to the synchronization arbiter: The internal clock counter stops counting; When the rising edge acquisition signal is acquired, the current counting value of the triggering edge is cleared, and the counting is restarted.
5. An apparatus for synchronizing a high speed clock based on a low speed clock, comprising at least one control processor and a memory communicatively coupled to the at least one control processor, the memory storing instructions executable by the at least one control processor to enable the at least one control processor to perform the method for synchronizing a high speed clock based on a low speed clock of any one of claims 3 to 4.
6. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the method of synchronizing a high-speed clock based on a low-speed clock according to any one of claims 3 to 4.

Description

System for synchronizing high-speed clock based on low-speed clock, method, device and medium thereof Technical Field The invention relates to the technical field of clock synchronization of ATE (automatic test equipment), in particular to a system for synchronizing a high-speed clock based on a low-speed clock, and a method, a device and a medium thereof. Background In ATE test equipment with a plurality of boards, clock sources used on different boards are different, and certain frequency offset can occur even if the clock sources are of the same frequency. Due to the existence of frequency offset, after long-time use, clocks on different boards can be misplaced, so that control and data among boards are misplaced, control asynchronism and data asynchronism are caused, and normal operation of ATE test equipment is affected. In some related arts, some schemes for synchronizing the internal clocks of the board using an external clock, for example, synchronizing one internal clock of the board using one external clock, or synchronizing a plurality of external clock sources onto one internal clock domain, are proposed, but this requires that the external clock be the same phase as the internal clock of the board, and that the frequency of the internal clock of the board be an integer multiple of the external clock. Therefore, the clock synchronization of the related art has high requirements on the external clock and the clock in the board card, resulting in high hardware complexity and design difficulty. Disclosure of Invention The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a system for synchronizing high-speed clocks based on low-speed clocks, a method, a device and a medium thereof, which can realize that one external clock synchronizes a plurality of internal clocks under the condition that the internal clocks and the external clocks have no limiting relation, thereby reducing hardware complexity. In a first aspect, an embodiment of the present invention provides a system for synchronizing a high-speed clock based on a low-speed clock, including: an external clock source for outputting an external clock; The receiving equipment comprises an external clock rising edge collector, an internal clock counter, a synchronous arbiter, an offset processing module, a synchronous processor and a post-processor, wherein the external clock rising edge collector is connected with the external clock source, the external clock rising edge collector and the internal clock counter are connected with the input end of the synchronous arbiter, the output end of the synchronous arbiter is connected with the input end of the offset processing module, the output end of the offset processing module is connected with the synchronous processor, and the synchronous processor is connected with the post-processor; The external clock rising edge collector responds to the rising edge of the external clock to output a rising edge collecting signal to the synchronous arbiter, the internal clock counter is used for counting the triggering edge of the internal clock, and after the counting value of the triggering edge reaches a preset period counting value, a period finishing signal is output, the period counting value is used for representing the multiple between the period of the external clock and the period of the internal clock, and the period of the external clock is larger than the period of the internal clock; the synchronous arbiter is used for triggering the offset processing module to send a synchronous trigger signal to the synchronous processor under the condition that the cycle completion signal and the rising edge acquisition signal do not arrive at the same time; wherein the synchronization processor adjusts a processing period of the post-processor to be the same as the external clock based on an offset between the internal clock and the external clock in response to the synchronization trigger signal. According to some embodiments of the invention, the offset processing module includes a stop processor, an output of the stop processor being connected to an input of the synchronization processor, the input of the stop processor being connected to an output of the synchronization arbiter; when the rising edge collecting signal is later than the period completing signal and reaches the synchronous arbiter, the synchronous arbiter is used for triggering the stopping processor to output a pause enabling signal to the synchronous processor, the synchronous processor responds to the pause enabling signal, determines pause duration according to the arrival time difference of the period completing signal and the rising edge collecting signal, and controls the back-stage processor to pause operation based on the pause duration; and when the external clock rising edge collector detects the next rising edge collecting signal, restarting the next p