CN-119621382-B - Memory system, method of operating the same, and computer readable storage medium

Abstract

The disclosure provides a memory system, an operation method thereof, a system and an operation method thereof, and a computer readable storage medium, wherein the memory system comprises an interface and an interface controller, the interface is connected with a host through a link, the interface controller is configured to determine whether link balancing needs to be conducted again or not based on temperature change of the memory system and error count of the interface, the error count comprises a first error count and a second error count, the first error count is the number of recoverable errors in a data packet received by the interface, the second error count is the number of times that the interface is switched between a normal working state and a recovery state, and the link balancing is triggered in response to the need of conducting the link balancing again.

Inventors

• QIN LINGJUN

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260512

Application Date

20230914

Claims (20)

1. 1. A memory system comprising an interface and an interface controller, the interface being coupled to a host via a link, the interface controller configured to: Acquiring an error count of the interface from the interface in response to an absolute value of a difference between a current temperature of the memory system and a temperature at a last time of link balancing being greater than a first preset value; determining whether link equalization needs to be carried out again or not based on the error count of the interface, wherein the error count comprises a first error count and a second error count, the first error count is the number of recoverable errors in a data packet received by the interface, and the second error count is the switching frequency of the interface between a normal working state and a recovery state; The link equalization is triggered in response to a need to re-perform the link equalization.
2. 2. The memory system of claim 1, wherein the interface controller is specifically configured to: and determining that the link equalization needs to be performed again in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value.
3. 3. The memory system of claim 2, wherein the interface controller is further configured to: in response to the transmission rate of the link being greater than or equal to 8GT/s, resetting the first error count and the second error count, and starting a timer; The current temperature of the memory system is obtained each time the timer reaches a timing period.
4. 4. The memory system of claim 2, wherein the interface controller is further configured to: and after the link equalization is successful, clearing the first error count and the second error count.
5. 5. The memory system of claim 1, wherein the interface controller is further configured to: Requesting the interface to transmit a pause and waiting for the interface to enter an idle state before triggering the link equalization; after the interface enters the idle state, a flag for executing equalization is set in a control register of the interface.
6. 6. The memory system of claim 5, wherein the interface is configured to: and responding to the mark for performing equalization, performing the link equalization, wherein the link equalization comprises sending a training ordered set to the host to inform the host of performing the link equalization.
7. 7. The memory system of claim 1, wherein the memory system comprises a memory device and a memory controller coupled to the memory device for controlling the memory device, wherein the memory controller comprises the interface and the interface controller or wherein the memory controller comprises the interface, and wherein the interface controller is external to the memory controller.
8. 8. The memory system of claim 1 wherein the interface is a high-speed serial computer expansion bus standard interface.
9. 9. A method of operation of a memory system, comprising: acquiring an error count of an interface from the interface in response to an absolute value of a difference between a current temperature of the memory system and a temperature at a last time of link equalization being greater than a first preset value; determining whether link equalization needs to be carried out again or not based on the error count of the interface, wherein the error count comprises a first error count and a second error count, the first error count is the number of recoverable errors in a data packet received by the interface, and the second error count is the switching frequency of the interface between a normal working state and a recovery state; The link equalization is triggered in response to a need to re-perform the link equalization.
10. 10. The method of claim 9, wherein the determining whether link equalization is needed based on the error count of the interface comprises: and determining that the link equalization needs to be performed again in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value.
11. 11. The method of operation of a memory system of claim 10, wherein the method of operation further comprises: in response to the transmission rate of the link being greater than or equal to 8GT/s, resetting the first error count and the second error count, and starting a timer; The current temperature of the memory system is obtained each time the timer reaches a timing period.
12. 12. The method of operation of a memory system of claim 10, wherein the method of operation further comprises: and after the link equalization is successful, clearing the first error count and the second error count.
13. 13. The method of operation of a memory system of claim 9, wherein the method of operation further comprises: Requesting the interface to transmit a pause and waiting for the interface to enter an idle state before triggering the link equalization; The triggering the link equalization includes: after the interface enters the idle state, a flag for executing equalization is set in a control register of the interface.
14. 14. The method of operation of a memory system of claim 13, wherein the method of operation further comprises: and in response to the flag to perform equalization, performing the link equalization, including sending a training ordered set to a host to inform the host to perform the link equalization.
15. 15. The system is characterized by comprising a host and a memory system, wherein the memory system comprises an interface and an interface controller, the host comprises a host interface, and the interface and the host interface are connected through a link; The interface controller is configured to acquire an error count of the interface from the interface in response to an absolute value of a difference between a current temperature of the memory system and a temperature at a last time of performing link equalization being greater than a first preset value, determine whether link equalization needs to be performed again based on the error count of the interface, wherein the error count comprises a first error count and a second error count, the first error count is the number of recoverable errors in a data packet received by the interface, and the second error count is the number of times the interface is switched between a normal working state and a recovery state; Triggering the link equalization in response to determining that the link equalization needs to be re-performed; the interface is configured to perform the link equalization including sending a training ordered set to the host interface to inform the host interface to perform the link equalization; the host interface is configured to receive the training ordered set and perform the link equalization.
16. 16. The system of claim 15, wherein the interface controller is specifically configured to: and determining that the link equalization needs to be performed again in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value.
17. 17. The system of claim 16, wherein the interface controller is further configured to: in response to the transmission rate of the link being greater than or equal to 8GT/s, resetting the first error count and the second error count, and starting a timer; The current temperature of the memory system is obtained each time the timer reaches a timing period.
18. 18. The system of claim 15, wherein the interface and the host interface are both high-speed serial computer expansion bus standard interfaces.
19. 19. A method of operation of a system, comprising: the interface controller responds that the absolute value of the difference value between the current temperature of the memory system and the temperature when the link balancing is carried out last time is larger than a first preset value, acquires an error count of the interface from the interface, determines whether the link balancing needs to be carried out again based on the error count of the interface, and triggers the link balancing in response to the link balancing needs to be carried out again; the interface performs the link equalization, including sending a training ordered set to a host interface to inform the host interface to perform the link equalization; the host interface receives the training ordered set and performs the link equalization.
20. 20. The method of claim 19, wherein the determining whether link equalization is needed based on the error count of the interface comprises: and determining that the link equalization needs to be performed again in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value.

Description

Memory system, method of operating the same, and computer readable storage medium Technical Field The present disclosure relates to the field of semiconductor technology, and in particular, to a memory system, an operating method thereof, a system, an operating method thereof, and a computer readable storage medium. Background In a system comprising a host and a memory system, the host and the memory system communicate according to a communication protocol, the host and the memory system are connected by a link, and both ends of the link are an interface on the host side and an interface on the memory system side. When the link enters an unstable state, a certain recovery mechanism is needed to make the link reenter a stable operation state. However, the link recovery mechanism in the related art has yet to be optimized. Disclosure of Invention In view of the above, embodiments of the present disclosure provide a memory system, an operating method thereof, a system operating method thereof, and a computer-readable storage medium for solving at least one of the problems in the prior art. In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows: In a first aspect, embodiments of the present disclosure provide a memory system comprising an interface and an interface controller, the interface being connected to a host by a link, the interface controller configured to: Determining whether link equalization is needed again based on the temperature change of the memory system and the error count of the interface, wherein the error count comprises a first error count and a second error count, the first error count is the number of recoverable errors in a data packet received by the interface, and the second error count is the number of times that the interface is switched between a normal working state and a recovery state; The link equalization is triggered in response to a need to re-perform the link equalization. In an alternative embodiment, the interface controller is specifically configured to: acquiring the current temperature of the memory system and the temperature of the memory system when the link balancing is performed last time; Acquiring the first error count and the second error count in response to the absolute value of the difference between the current temperature and the temperature at the last time of link equalization being greater than a first preset value; and determining that the link equalization needs to be performed again in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value. In an alternative embodiment, the interface controller is further configured to: in response to the transmission rate of the link being greater than or equal to 8GT/s, resetting the first error count and the second error count, and starting a timer; The current temperature of the memory system is obtained each time the timer reaches a timing period. In an alternative embodiment, the interface controller is further configured to: and after the link equalization is successful, clearing the first error count and the second error count. In an alternative embodiment, the interface controller is further configured to: Requesting the interface to transmit a pause and waiting for the interface to enter an idle state before triggering the link equalization; after the interface enters the idle state, a flag for executing equalization is set in a control register of the interface. In an alternative embodiment, the interface is configured to: and responding to the mark for performing equalization, performing the link equalization, wherein the link equalization comprises sending a training ordered set to the host to inform the host of performing the link equalization. In an alternative embodiment, the memory system comprises a memory device and a memory controller coupled to the memory device for controlling the memory device, wherein the memory controller comprises the interface and the interface controller, or the memory controller comprises the interface, and the interface controller is externally arranged on the memory controller. In an alternative embodiment, the interface is a high-speed serial computer expansion bus standard interface. In a second aspect, embodiments of the present disclosure provide a method of operating a memory system, comprising: Determining whether link equalization is needed to be performed again based on temperature change of the memory system and error count of an interface, wherein the error count comprises a first error count and a second error count, the first error count is the number of recoverable errors in a data packet received by the interface, and the second error count is the number of times that the interface is switched between a normal working state and a recovery state; The link equalization is triggered in response to a