CN-119645185-B - High-precision reference voltage circuit

Abstract

The invention provides a high-precision reference voltage circuit, which comprises an anti-interference circuit module, a gain circuit module and an amplifying buffer circuit module, so that the output voltage of the circuit has higher precision and larger output voltage swing while having a lower temperature coefficient. The circuit also comprises a bias circuit and a voltage stabilizing output circuit. The bias circuit comprises an anti-interference circuit, so that the bias circuit can work normally under a high-frequency electromagnetic interference environment. The bias circuit is arranged based on the circuit structure, so that the output bias voltage is stable and unchanged. The voltage stabilizing output circuit comprises a gain circuit, so that the system has higher gain and further has higher power supply rejection ratio. The amplifying buffer circuit in the voltage stabilizing output circuit has a frequency compensation function, so that the system keeps stable operation in a low frequency range and a high frequency range. Meanwhile, the amplifying buffer circuit is based on the circuit structure, so that the system has lower output impedance, the current output capacity of the system is improved, and the output voltage has larger voltage swing.

Inventors

• LIU HUI
• YU JUNFENG
• SU FUNAN
• LIU ZHENPENG

Assignees

• 深圳市亿方电子有限公司

Dates

Publication Date

20260512

Application Date

20241204

Claims (1)

1. 1. The high-precision reference voltage circuit is characterized by comprising a bias circuit (1) and a voltage stabilizing output circuit (2); The bias circuit (1) is connected with the voltage stabilizing output circuit (2), the bias circuit (1) outputs accurate and stable bias voltage (Vbe) to the voltage stabilizing output circuit (2), the bias circuit (1) comprises an anti-interference circuit, the bias circuit (1) can normally work in a high-frequency electromagnetic interference environment, the bias circuit (1) can effectively shield the influence caused by power voltage jitter based on circuit structure setting, the output bias voltage is stable and unchanged, the voltage stabilizing output circuit (2) comprises a gain circuit, a system has higher gain and further has higher power supply rejection ratio, an amplifying buffer circuit in the voltage stabilizing output circuit (2) has a frequency compensation function, the system can keep stable running in a low-frequency range and a high-frequency range, and a combining circuit in the voltage stabilizing output circuit (2) is mainly used for generating a reference voltage Vrt with a lower temperature coefficient; The bias circuit (1) comprises an anti-interference circuit (11) and a bias voltage circuit (12); the anti-interference circuit (11) is connected with the bias voltage circuit (12), and the anti-interference circuit (11) provides an anti-interference voltage Vgs for the bias voltage circuit (12) so that the bias voltage circuit (12) can normally work in a high-frequency electromagnetic interference environment; The voltage stabilizing output circuit (2) comprises a gain circuit (21), an amplifying buffer circuit (22) and a combining circuit (23); The gain circuit (21) is connected with the amplifying buffer circuit (22), the gain circuit (21) outputs a high gain voltage Veh to the amplifying buffer circuit (22), the amplifying buffer circuit (22) can stably output the high gain voltage in a low frequency range and a high frequency range through frequency compensation and enables the output voltage to have larger voltage swing, the amplifying buffer circuit (22) is connected with the combining circuit (23), the amplifying buffer circuit (22) outputs the voltage Vpr to the combining circuit (23), and the combining circuit (23) processes the output voltage Vpr and outputs a reference voltage Vrt with a lower temperature coefficient; The anti-interference circuit (11) comprises a self-bias power supply circuit (111) and a current-limiting output circuit (112), wherein the self-bias power supply circuit (111) is connected with the current-limiting output circuit (112), and the self-bias power supply circuit (111) outputs an anti-interference voltage Vgs to the current-limiting output circuit (112); the bias voltage circuit (12) comprises a shielding circuit (121) and a load circuit (122), wherein the shielding circuit (121) is connected with the load circuit (122), and the shielding circuit (121) outputs and outputs a precise and stable bias voltage (Vbe) through the load circuit (122); The gain circuit (21) comprises a coupling circuit (211) and a constant current area circuit (212), wherein the coupling circuit (211) is connected with the constant current area circuit (212), the constant current area circuit (212) enables MOS (metal oxide semiconductor) tubes in the coupling circuit (211) to work in a constant current area through providing bias current, the coupling circuit (211) generates and outputs high gain voltage Veh to the amplifying buffer circuit (22) and increases the power supply rejection ratio of the voltage stabilizing output circuit (2) so as to improve the system output precision, and the coupling circuit (211) participates in the generation of low temperature coefficient reference voltage through the connection with the combining circuit (23); the amplifying buffer circuit (22) comprises a frequency compensation circuit (221) and a common source amplifying circuit (222), wherein the frequency compensation circuit (221) is connected with the common source amplifying circuit (222), and the frequency compensation circuit (221) generates a system main pole to maintain the stable operation of the common source amplifying circuit (222) in a high frequency band; The combining circuit (23) comprises an input circuit (231), a branch current circuit (232) and an output circuit (233), wherein the input circuit (231) is connected with the branch current circuit (232), the input circuit (231) provides working voltage for the branch current circuit (232) to enable the branch current circuit to generate branch current Ib and current Ic respectively, the input circuit (231) is connected with the output circuit (233), the input circuit (231) copies the current Ib and the current Ic in the branch current circuit (232) into the output circuit (233) to combine and generate current Io, and the output circuit (233) generates reference voltage Vrt based on the current Io; The self-bias power supply circuit (111) comprises a MOS tube M1, a MOS tube M2, a MOS tube M3 and a MOS tube M4; the source electrode of the MOS tube M1 is connected with the power supply VDD, the grid electrode of the MOS tube M1 is connected with the grid electrode of the MOS tube M2, the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M2, the grid electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M2, the source electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M3, the drain electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M3, the source electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M4, the drain electrode of the MOS tube M4 is connected with the source electrode of the MOS tube M3, and the source electrode of the MOS tube M4 is grounded; The coupling circuit (211) comprises a MOS tube M14, a MOS tube M15, a MOS tube M17 and a MOS tube M18; The source electrode of the MOS tube M14 is connected with the power supply VDD, the grid electrode of the MOS tube M14 is connected with the grid electrode of the MOS tube M17, the drain electrode of the MOS tube M14 is connected with the drain electrode of the MOS tube M15, the drain electrode of the MOS tube M15 is connected with the drain electrode of the MOS tube M28, the source electrode of the MOS tube M15 is connected with the drain electrode of the MOS tube M16, the source electrode of the MOS tube M17 is connected with the source electrode of the MOS tube M14, the gate electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M15, the drain electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M18, the gate electrode of the MOS tube M18 is connected with the drain electrode of the MOS tube M27, and the source electrode of the MOS tube M18 is connected with the drain electrode of the MOS tube M19; The constant current region circuit (212) comprises a MOS tube M19, a MOS tube M16 and a port VCLS; The drain electrode of the MOS tube M16 is connected with the source electrode of the MOS tube M19, the gate electrode of the MOS tube M16 is connected with the port VCLS, and the source electrode of the MOS tube M16 is grounded, the drain electrode of the MOS tube M19 is connected with the source electrode of the MOS tube M18, the gate electrode of the MOS tube M19 is connected with the drain electrode of the MOS tube M19, and the source electrode of the MOS tube M19 is connected with the source electrode of the MOS tube M15; the frequency compensation circuit (221) comprises a resistor R1, a capacitor C1, a MOS tube M20, a MOS tube M21 and a MOS tube M24; The source electrode of the MOS tube M20 is connected with the source electrode of the MOS tube M17, the grid electrode of the MOS tube M20 is connected with the drain electrode of the MOS tube M17, the drain electrode of the MOS tube M20 is connected with the drain electrode of the MOS tube M21, the upper end of the resistor R1 is connected with the lower end of the capacitor C1, the lower end of the resistor R1 is connected with the drain electrode of the MOS tube M20, the lower end of the capacitor C1 is connected with the upper end of the resistor R1, the drain electrode of the MOS tube M21 is connected with the drain electrode of the MOS tube M20, the grid electrode of the MOS tube M21 is connected with the source electrode of the MOS tube M22, the drain electrode of the MOS tube M24 is connected with the source electrode of the MOS tube M20, the grid electrode of the MOS tube M24 is connected with the drain electrode of the MOS tube M21, and the source electrode of the MOS tube M24 is connected with the source electrode of the MOS tube M25; The common source amplifying circuit (222) comprises a MOS tube M22, a MOS tube M23, a MOS tube M25 and a MOS tube M26; The source electrode of the MOS tube M22 is connected with the source electrode of the MOS tube M21, the grid electrode of the MOS tube M22 is connected with the grid electrode of the MOS tube M25, the drain electrode of the MOS tube M22 is connected with the drain electrode of the MOS tube M23, the drain electrode of the MOS tube M23 is connected with the grid electrode of the MOS tube M16, the source electrode of the MOS tube M23 is grounded, the source electrode of the MOS tube M25 is connected with the grid electrode of the MOS tube M27, the grid electrode of the MOS tube M25 is connected with the drain electrode of the MOS tube M22, the drain electrode of the MOS tube M25 is connected with the drain electrode of the MOS tube M26, the gate electrode of the MOS tube M26 is connected with the drain electrode of the MOS tube M26, and the source electrode of the MOS tube M26 is grounded; The branch current circuit (232) comprises a resistor R2, a resistor R3, a resistor R4, a triode Q1, a triode Q2, a triode Q3 and a triode Q4; The upper end of the resistor R2 is connected with the drain electrode of the MOS transistor M27, the lower end of the resistor R2 is connected with the base electrode of the triode Q1, the emitter electrode of the triode Q1 is connected with the drain electrode of the MOS transistor M27, the base electrode of the triode Q1 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q2 is connected with the lower end of the resistor R2, the base electrode of the triode Q2 is connected with the collector electrode of the triode Q2, the collector electrode of the triode Q2 is grounded, the upper end of the resistor R3 is connected with the drain electrode of the MOS transistor M28, the lower end of the resistor R3 is connected with the emitter electrode of the triode Q3, the upper end of the resistor R4 is connected with the base electrode of the triode Q3, the emitter electrode of the triode Q3 is connected with the lower end of the resistor R3, the collector electrode of the triode Q3 is connected with the emitter electrode of the triode Q4, the emitter electrode of the triode Q4 is connected with the collector electrode of the triode Q4, and the collector electrode of the triode Q4 is grounded; the output circuit (233) comprises a MOS tube M30, a MOS tube M31 and a port VOUT; the drain electrode of the MOS tube M30 is connected with the port VOUT, the grid electrode of the MOS tube M30 is connected with the drain electrode of the MOS tube M30, the source electrode of the MOS tube M30 is connected with the drain electrode of the MOS tube M31, the drain electrode of the MOS tube M31 is connected with the source electrode of the MOS tube M30, the grid electrode of the MOS tube M31 is connected with the grid electrode of the MOS tube M30, and the source electrode of the MOS tube M31 is grounded.

Description

High-precision reference voltage circuit Technical Field The invention relates to the technical field of integrated circuits, in particular to a high-precision reference voltage circuit. Background The reference voltage circuit provides a precise and stable reference voltage for the integrated circuit system as a reference voltage or threshold value for the integrated circuit system. In order to make the output voltage of the reference voltage circuit have a low temperature coefficient, temperature compensation is generally performed by using a curvature compensation technique, a band gap linearization technique, or the like. However, the operational amplifier circuit adopted in the temperature offset compensation scheme based on the resistance ratio has larger offset voltage, and seriously affects the output voltage precision of the reference voltage circuit. And in integrated circuit systems, a plurality of high-frequency switching tubes are usually arranged, and the high-frequency electromagnetic interference generated by the high-frequency switching tubes has a great influence on the output precision of a reference voltage circuit. Disclosure of Invention The invention solves the problem of providing a high-precision reference voltage circuit, which comprises an anti-interference circuit module, a gain circuit module and an amplifying buffer circuit module, so that the output voltage of the circuit has a lower temperature coefficient and higher precision and larger output voltage swing. In order to solve the problems, the high-precision reference voltage circuit provided by the invention comprises a bias circuit and a voltage stabilizing output circuit. The bias circuit is connected with the voltage stabilizing output circuit and outputs accurate and stable bias voltage to the voltage stabilizing output circuit. The bias circuit comprises an anti-interference circuit, so that the bias circuit can work normally under a high-frequency electromagnetic interference environment. The bias circuit is arranged based on the circuit structure, so that the influence caused by power supply voltage jitter can be effectively shielded, and the output bias voltage is stable and unchanged. The voltage stabilizing output circuit comprises a gain circuit, so that the system has higher gain and further has higher power supply rejection ratio. The amplifying buffer circuit in the voltage stabilizing output circuit has a frequency compensation function, so that the system keeps stable operation in a low frequency range and a high frequency range. Meanwhile, the amplifying buffer circuit is based on the circuit structure, so that the system has lower output impedance, the current output capacity of the system is improved, and the output voltage has larger voltage swing. The combining circuit in the regulated output circuit is mainly used for generating a reference voltage with a lower temperature coefficient. The biasing circuit includes a port VPES. The regulated output circuit includes ports VCLS and VOUT. Port VPES is connected to port VCLS for transmitting the bias voltage Vbe. The port VOUT is a system output port for outputting the reference voltage Vrt. The bias circuit comprises an anti-interference circuit and a bias voltage circuit. The anti-interference circuit is connected with the bias voltage circuit and provides anti-interference voltage for the bias voltage circuit, so that the bias voltage circuit can work normally in a high-frequency electromagnetic interference environment. The bias voltage circuit outputs accurate and stable bias voltage to the voltage stabilizing output circuit The voltage stabilizing output circuit comprises a gain circuit, an amplifying buffer circuit and a combining circuit. The gain circuit is connected with the amplifying buffer circuit and outputs high gain voltage to the amplifying buffer circuit. The amplifying buffer circuit can stably output high-gain voltage in a low frequency range and a high frequency range through frequency compensation, and the output voltage has a larger voltage swing. The amplifying buffer circuit is connected with the combining circuit, and outputs the voltage to the combining circuit, and the combining circuit processes the voltage and outputs the reference voltage with lower temperature coefficient. Compared with the prior art, the high-precision reference voltage circuit has the beneficial effects that the high-precision reference voltage circuit comprises the bias circuit and the voltage stabilizing output circuit. The bias circuit outputs accurate and stable bias voltage to the voltage stabilizing output circuit, so that the voltage stabilizing output circuit has higher stability and precision. The bias circuit comprises an anti-interference circuit, so that the bias circuit can work normally under a high-frequency electromagnetic interference environment. The bias circuit is arranged based on the circuit structure, so that the influence caused by p