Search

CN-119694254-B - Display control method, circuit, electronic device, and computer-readable storage medium

CN119694254BCN 119694254 BCN119694254 BCN 119694254BCN-119694254-B

Abstract

The application provides a display control method, a circuit, electronic equipment and a computer readable medium, and relates to the technical field of digital image processing. The method comprises the steps of storing data to be converted into a first storage unit, converting the data to be converted into first packet data and second packet data in the first storage unit, storing storage signal control packet data into a second storage unit, transmitting transmission signal control packet data to a primary circuit, wherein a storage signal comprises a first storage sub-signal and a second storage sub-signal, the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal, the second storage sub-signal is triggered by delaying a preset time period when the first storage sub-signal is finished, triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent. By optimizing the time sequence configuration of the control signals, the data flipping and waiting time are reduced, the invalid working time can be effectively reduced, and the power consumption of the chip is reduced.

Inventors

  • QIN MUJIN
  • LV HENG

Assignees

  • 合肥芯颖科技有限公司

Dates

Publication Date
20260508
Application Date
20250213

Claims (7)

  1. 1. A display control method, characterized in that the display control method comprises: Storing data to be converted into a first storage unit, and converting the data to be converted into first packet data and second packet data in the first storage unit; Controlling the first packet data and the second packet data to be stored in a second storage unit through a storage signal, wherein the storage signal comprises a first storage sub-signal and a second storage sub-signal; Controlling the first packet data and the second packet data to be transmitted to a primary circuit through a transmission signal, wherein the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal; The second storage sub-signal is triggered by delaying a preset period when the first storage sub-signal is ended, wherein the trigger time points of the first storage sub-signal and the first transmission sub-signal are consistent; the display control method further comprises the following steps: The transmission signal controls the first packet data and the second packet data to pass through the primary circuit and then transmits the first packet data and the second packet data to the secondary circuit; Wherein the first packet data includes a first type of data and a second type of data, and the second packet data includes a third type of data and a fourth type of data; Controlling the transmission of the first packet data and the second packet data to a primary circuit by a transmission signal, further comprising: transmitting the first type data and/or the third type data to the secondary circuit when the transmission signal is at a high level; and transmitting the second type data and/or the fourth type data to the secondary circuit under the condition that the transmission signal is low level.
  2. 2. The display control method according to claim 1, wherein the controlling of the first packet data and the second packet data to be stored in the second storage unit by the storage signal includes: And controlling the first packet data to be stored in the second storage unit from the first storage unit through the first storage sub-signal, and controlling the second packet data to be stored in the second storage unit from the first storage unit through the second storage sub-signal.
  3. 3. The display control method according to claim 1, wherein the controlling the transmission of the first packet data and the second packet data to the primary circuit by the transmission signal includes: Controlling the first packet data to be transferred from the second storage unit into the primary circuit through the first transmission sub-signal; and controlling the second packet data to be transmitted into the primary circuit from the second storage unit through the second transmission sub-signal.
  4. 4. The display control method according to claim 1, wherein storing the data to be converted into a first storage unit and converting the data to be converted into first packet data and second packet data in the first storage unit, includes: Preprocessing the original data to obtain the data to be converted; Temporarily storing the data to be converted to the first storage unit; And under the condition that the first storage unit receives all the data to be converted, dividing the data to be converted into the first packet data and the second packet data through the first storage unit.
  5. 5. A display control circuit is characterized by comprising a first storage unit, a second storage unit and a primary circuit; The first storage unit is configured to store data to be converted and receive a storage signal to execute corresponding operation, wherein the storage signal comprises a first storage sub-signal and a second storage sub-signal; the first storage unit receives the first storage sub-signal to divide the data to be converted into first packet data and second packet data; The second storage unit is configured to transmit the first packet data and the second packet data to a primary circuit after receiving a transmission signal; the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal; The second storage sub-signal is triggered by delaying a preset period when the first storage sub-signal is ended, wherein the trigger time points of the first storage sub-signal and the first transmission sub-signal are consistent; the display control circuit also comprises a secondary circuit; The secondary circuit is configured to receive and convert the first packet data and the second packet data and then output a display voltage; Wherein the first packet data includes a first type of data and a second type of data, and the second packet data includes a third type of data and a fourth type of data; Wherein the second storage unit receives the transmission signal and then transmits the first packet data and the second packet data to a primary circuit, and further comprises: transmitting the first type data and/or the third type data to the secondary circuit when the transmission signal is at a high level; and transmitting the second type data and/or the fourth type data to the secondary circuit under the condition that the transmission signal is low level.
  6. 6. An electronic device comprising a memory and a processor, the memory having stored therein program instructions which, when executed by the processor, perform the steps of the method of any of claims 1-4.
  7. 7. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein computer program instructions which, when executed by a processor, perform the steps of the method according to any of claims 1-4.

Description

Display control method, circuit, electronic device, and computer-readable storage medium Technical Field The present application relates to the field of digital image processing technology, and in particular, to a display control method, a circuit, an electronic device, and a computer readable storage medium. Background With the continuous development of display technology, AMOLED display screens are widely used in electronic devices such as smart phones and tablet computers due to the advantages of high contrast, wide color gamut, low power consumption and the like. In order to improve the resolution of AMOLED displays, penTile technology is typically used. The PenTile technology realizes higher pixel density through a special sub-pixel arrangement mode, thereby improving the display effect. In the AMOLED display screen, the driving chip is required to process a large amount of picture data. In general, the image data sent by the host is real image data, and the driving chip processes the real image data into the subpixel data arranged in Pentile through a subpixel rendering technology (subpixel rendering, abbreviated as SPR). This approach, while increasing the display resolution, also increases the complexity of the data processing. However, this design has certain problems in the data transmission process. The driving chip is required to transmit the data of the sub-pixel 1 or the data of the sub-pixel 2 to the gray scale voltage converting circuit in a row of display time in a time period. It is a common practice to select the subpixel data to be transferred in the current period by a control signal which transfers the subpixel 1 data when high and the subpixel 2 data when low. When the data of the sub-pixel 1 and the data of the sub-pixel 2 are switched, invalid data flip exists in a period of time, so that the gray scale voltage conversion circuit is invalid in a period of time, and the driving chip is increased in power consumption in a period of time. Disclosure of Invention Accordingly, an object of an embodiment of the present application is to provide a display control method, which reduces data flip and waiting time by optimizing timing configuration of control signals, so as to effectively reduce invalid working time and reduce chip power consumption. So as to solve the problems of multiple invalid working time and large power consumption of chips in the prior art. The display control method comprises the steps of storing data to be converted into first packet data and second packet data in a first storage unit, controlling the first packet data and the second packet data to be stored in the second storage unit through storage signals, controlling the first packet data and the second packet data to be transmitted to a primary circuit through transmission signals, wherein the transmission signals comprise a first transmission sub-signal and a second transmission sub-signal, delaying triggering of the second storage sub-signal by a preset time period when the first storage sub-signal is finished, enabling triggering time points of the first storage sub-signal and the first transmission sub-signal to be consistent, and enabling triggering time points of the second storage sub-signal and the second transmission sub-signal to be consistent. In the above implementation, the preliminary storage and grouping operations are first completed in the first storage unit. And after the first storage unit completely receives the data to be converted in the first storage unit and converts the data to be converted into first packet data and second packet data, the first packet data and the second packet data are controlled to be respectively stored in the second storage unit, and then the first packet data and the second packet data are controlled to be transmitted to the primary circuit through a transmission signal, wherein the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal. And the triggering of the second storage sub-signal is delayed for a preset period after the first storage sub-signal is finished, the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and the triggering time points of the second storage sub-signal and the second transmission sub-signal are also consistent, so that the ordered storage and transmission of data are realized, the stability and the reliability of the overall display control method are improved, the time sequence of each signal can be further allocated, the invalid working time of a circuit is reduced, and the power consumption of a chip is reduced. Optionally, the display control method further comprises the step that the transmission signal controls the first packet data and the second packet data to pass through the primary circuit and then transmits the first packet data and the second packet data to the secondary circuit, and the secondary circuit converts the fi