CN-119763632-B - Memory operation method and memory chip

Abstract

The memory operation method and the memory chip provided by the invention comprise the steps of obtaining the operation depth, wherein the operation depth is determined in a wafer test and stored in a memory cell, the operation depth represents the threshold voltage change level of the memory cell after the operation is performed, and when the operation is performed, the operation depth is used for performing depth verification until the operation depth is reached. The invention can accurately test the operation depth of the memory chip, further guide the actual operation by utilizing the operation depth, realize the purpose of accurately controlling the operation effect and avoid the problem that the threshold voltage of the memory cell becomes complex and uncontrollable.

Inventors

• FENG GUOYOU

Assignees

• 普冉半导体(上海)股份有限公司

Dates

Publication Date

20260508

Application Date

20241212

Claims (9)

1. 1. A memory operation method applied to a memory chip including a plurality of memory cells, the method comprising: The method comprises the steps of obtaining operation depth, wherein the operation depth comprises the steps of executing a continuous operation process, confirming whether a set reference depth value is reached after the execution is finished, repeating the continuous operation process after the adjustment of the reference depth value if the set reference depth value is not reached, otherwise stopping the test, taking the current reference depth value as the operation depth corresponding to the operation process and writing the operation depth into a memory chip, wherein the operation depth is determined in a wafer test and stored in a memory unit; When an operation is performed, a depth check is performed using the operation depth until the operation depth is reached.
2. 2. The memory operation method according to claim 1, wherein performing an operation using the operation depth for depth verification until the operation depth is reached, comprises: after an operation instruction is obtained, executing the operation indicated by the operation instruction for a plurality of times on a storage unit to be operated, and confirming whether the operation depth required to be met by the operation is reached after each operation; If not, executing the operation next time, otherwise ending the operation.
3. 3. The memory operation method according to claim 1, wherein obtaining an operation depth further comprises: The respective operating depth of each die is obtained.
4. 4. The memory operation method according to claim 1, wherein obtaining an operation depth further comprises: If the operation process is an erasing process, the memory cell is adjusted to a uniform logic state in the erasing process, and then the erasing operation is executed.
5. 5. The memory operation method according to claim 1, wherein obtaining an operation depth further comprises: if the operation process is a programming process, the residual data of the memory cell is cleared first and then the programming operation is executed in the programming process.
6. 6. The memory operation method according to claim 1, wherein obtaining an operation depth further comprises: after the operation process is completed, checking whether each operation position is correctly operated.
7. 7. The memory operation method according to claim 1, wherein when an operation is performed, depth verification is performed using the operation depth until the operation depth is reached, further comprising: if the operation is erasing, the memory cell to be operated is pre-programmed after receiving the erasing instruction.
8. 8. The memory operation method according to claim 1, wherein when an operation is performed, depth verification is performed using the operation depth until the operation depth is reached, further comprising: And after each time of operation, carrying out consistency check on the data of the storage unit to be operated.
9. 9. A memory chip comprising a plurality of memory cells, the memory chip being configured to perform the memory operation method of any one of claims 1-8.

Description

Memory operation method and memory chip Technical Field The invention relates to the technical field of memory chips, in particular to a memory operation method and a memory chip. Background Charge trapping flash memory (ChargeTrappingMemory), also known as charge trapping memory, is one of the advanced memory technologies that can use traps in semiconductor materials to trap and hold charges (electrons or holes). When an erase operation or a program operation is performed, the trap state of the memory cells in such a memory chip is changed, and the newly injected charges may escape rapidly in an initial stage, but the rate of such escape may exhibit an exponentially decreasing trend over time. Eventually, the rate of charge escape will slow down to a steady state, ensuring data stability. However, it is the uncertainty of charge escape that makes it difficult to accurately control the operation depth for existing operation modes such as erase operation or program operation of such memory chips like charge trapping type flash memory, which may cause the threshold voltage of the memory cell to be difficult to reach a desired level, and such uncontrollability may affect the performance of the memory chip. Disclosure of Invention Accordingly, an object of the present invention is to provide a memory operation method and a memory chip, which can measure depth information that the memory chip needs to reach when performing a specific operation in advance, and can call the depth information to accurately control an operation depth during a data operation, so as to avoid that a threshold voltage of a memory cell becomes complicated and uncontrollable. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: In a first aspect, the invention provides a memory operation method applied to a memory chip, wherein the memory chip comprises a plurality of memory cells, and the method comprises the steps of obtaining an operation depth, wherein the operation depth is determined in a wafer test and stored in the memory cells, the operation depth represents the threshold voltage change level of the memory cells after operation, and when the operation is executed, the operation depth is used for depth verification until the operation depth is reached. In an alternative embodiment, when the operation is executed, the operation depth is used for carrying out the depth verification until the operation depth is reached, and the method comprises the steps of executing the operation indicated by the operation instruction for a plurality of times on a storage unit to be operated after the operation instruction is obtained, confirming whether the operation depth required to be satisfied by the operation is reached after each operation, and executing the next operation if not, otherwise ending the operation. In an alternative embodiment, obtaining the operation depth comprises the steps of executing a continuous operation process, confirming whether a set reference depth value is reached after the execution is finished, if not, repeating the continuous operation process after adjusting the reference depth value, otherwise, stopping the test, taking the current reference depth value as the operation depth corresponding to the operation process, and writing the current reference depth value into a memory chip. In an alternative embodiment, obtaining the operational depth further comprises obtaining a respective operational depth for each die. In an alternative embodiment, the method further comprises the steps of adjusting the memory cells to a uniform logic state in the process of performing the erase operation if the operation process is an erase process, and then performing the erase operation. In an alternative embodiment, the method further comprises the steps of clearing residual data of the memory cells in the programming process and then performing the programming operation if the operation process is the programming process. In an alternative embodiment, the obtaining of the operation depth further comprises checking whether each operation position is correctly operated after the operation process is performed. In an alternative embodiment, when performing the operation, performing the depth verification by using the operation depth until the operation depth is reached, and if the operation is an erase, pre-programming the memory cell to be operated after receiving the erase command. In an alternative embodiment, when executing the operation, the depth check is performed by using the operation depth until the operation depth is reached, and the method further comprises performing consistency check on the data of the storage unit to be operated after each time the operation is completed. In a second aspect, the present invention provides a memory chip comprising a plurality of memory cells for performing the memory operation method according to any one of the preceding embodiments. Acco