CN-119789497-B - Semiconductor device and manufacturing method thereof

CN119789497BCN 119789497 BCN119789497 BCN 119789497BCN-119789497-B

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for simplifying the manufacturing process of manufacturing at least five kinds of gate-all-around transistors with different absolute values of threshold voltages and reducing the manufacturing difficulty of the semiconductor device. The semiconductor device includes a semiconductor substrate, and at least five types of gate-all-around transistors disposed on the semiconductor substrate. The different types of gate-all-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate. In the different types of gate-all-around transistors, at least part of the nanostructure included in the different channel regions is made of different materials, and the different parts of the nanostructure included in the different channel regions are distributed in a staggered manner along the thickness direction of the semiconductor substrate. In at least five kinds of gate-all-around transistors, the different channel regions of at least two kinds of gate-all-around transistors comprise the same material of the portion of the nanostructure, and the portions of the nanostructure comprising the different channel regions are aligned along the thickness direction of the semiconductor substrate.

Inventors

LI YONGLIANG
ZHOU YU

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260505
Application Date: 20241226

Claims (10)

1. The semiconductor device is characterized by comprising a semiconductor substrate and at least five types of gate-all-around transistors arranged on the semiconductor substrate, wherein the different types of gate-all-around transistors are distributed at intervals along the direction parallel to the surface of the semiconductor substrate; the gate-all-around transistors comprise at least five kinds of gate-all-around transistors, wherein at least part of the nano structures included in different channel regions are different in material, and parts of the nano structures included in different channel regions are distributed in a staggered manner along the thickness direction of the semiconductor substrate; And in the at least five types of the gate-all-around transistors, the surface heights of the semiconductor substrate at the area where at least two types of the gate-all-around transistors are located are different.
2. The semiconductor device of claim 1, wherein in the case where the nanostructures included in the channel region in at least two types of the gate-all-around transistors have at least two materials, thicknesses of portions of different materials in the nanostructures are the same.
3. The semiconductor device according to claim 1, wherein the material of the nanostructure included in the gate-all-around transistor includes Si 1-x Ge x , 0≤x≤1; In different types of the gate-all-around transistors, the different channel regions comprise nanostructures with different germanium content in at least part of the material.
4. A semiconductor device according to claim 3, wherein the different channel regions comprise nanostructures of which at least part of the material have germanium content that differs by at least 20% in the different types of the gate-all-around transistors.
5. The semiconductor device of claim 1, wherein among the at least five types of gate-all-around transistors, different channel regions belonging to at least two types of the gate-all-around transistors comprise different thicknesses of nanostructures.
6. The semiconductor device according to any one of claims 1 to 5, wherein portions of the channel regions included in the different types of the gate-all-around transistors, which are the same in material, are integrally formed; and/or the materials of the gate stack structures included in different types of the ring gate transistors are the same.
7. A method of manufacturing a semiconductor device, comprising: Providing a semiconductor substrate; Forming at least five kinds of gate-all-around transistors on the semiconductor substrate, wherein the gate-all-around transistors of different kinds are distributed at intervals along the direction parallel to the surface of the semiconductor substrate, at least part of the nano structures included in different channel regions are different in materials in the gate-all-around transistors of different kinds, and the part of the nano structures included in the channel regions are distributed in a staggered manner along the thickness direction of the semiconductor substrate; And in the at least five types of the gate-all-around transistors, the surface heights of the semiconductor substrate at the area where at least two types of the gate-all-around transistors are located are different.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the forming at least five types of gate-all-around transistors on the semiconductor substrate comprises: Forming at least five fin structures which are distributed at intervals and have the same structure on the semiconductor substrate, wherein each fin structure comprises at least three semiconductor layers which are alternately stacked and are made of different materials along the thickness direction of the semiconductor substrate; Forming a first mask structure transverse to each type of fin structure; Processing the portions of each fin structure exposed out of the first mask structure respectively to form a source region and a drain region of each gate-all-around transistor; Removing at least part of the first mask structure; Selectively removing part of the semiconductor layers in one type of fin structure to form channel regions included in corresponding types of gate-all-around transistors in the other type of fin structure; And forming a gate stack structure surrounding the periphery of a channel region included in each type of the gate-all-around transistors.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the gate around transistor of the portion of the semiconductor layer located at the bottom layer is a target-like gate around transistor; after removing at least part of the first mask structure, before forming the gate stack structure around the periphery of a channel region included in each type of gate-all-around transistor, the method for manufacturing the semiconductor device further comprises selectively removing a part of the thickness of the semiconductor substrate located below the target type of gate-all-around transistor.
10. The method of manufacturing a semiconductor device according to claim 8, wherein forming at least five fin structures which are spaced apart and have the same structure on the semiconductor substrate comprises: Forming at least three semiconductor layers which are alternately stacked in a thickness direction of the semiconductor substrate and are different in material on the semiconductor substrate; and selectively etching at least the at least three semiconductor layers which are alternately stacked to form the at least five fin structures.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background The gate stack included in the gate-all-around transistor is formed not only on the top and the side wall of the channel but also on the bottom of the channel, so that the gate-all-around transistor has the advantages of higher gate control capability and the like compared with the planar transistor and the fin field effect transistor. However, in the case where the semiconductor device includes at least two types of gate-all-around transistors formed on the semiconductor substrate and the absolute values of threshold voltages of the at least two types of gate-all-around transistors are different, the process of manufacturing the two types of gate-all-around transistors obtained by the existing manufacturing method is complicated and requires a high level, resulting in a high difficulty in manufacturing the semiconductor device. Disclosure of Invention The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for simplifying the manufacturing process of manufacturing at least five types of gate-all-around transistors with different absolute values of threshold voltages and reducing the manufacturing difficulty of the semiconductor device. In order to achieve the above object, in a first aspect, the present invention provides a semiconductor device including a semiconductor substrate, and at least five kinds of gate-all-around transistors provided on the semiconductor substrate. The different types of gate-all-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate. In the different types of gate-all-around transistors, at least part of the nanostructure included in the different channel regions is made of different materials, and the different parts of the nanostructure included in the different channel regions are distributed in a staggered manner along the thickness direction of the semiconductor substrate. In at least five kinds of gate-all-around transistors, the different channel regions of at least two kinds of gate-all-around transistors comprise the same material of the portion of the nanostructure, and the portions of the nanostructure comprising the different channel regions are aligned along the thickness direction of the semiconductor substrate. Under the condition of adopting the technical scheme, in the semiconductor device provided by the invention, at least part of materials of the nanostructures included in different channel regions are different in different types of gate-all-around transistors, and at least part of the nanostructures with different materials may have different conductive characteristics, so that the nanostructures included in the different types of gate-all-around transistors are manufactured by adopting at least part of different semiconductor materials, the channel regions of the different types of gate-all-around transistors have different conduction characteristics, and the gate-all-around transistors have threshold voltages with different absolute values, so that corresponding working requirements are met. In addition, the different channel regions comprise different parts of the nanostructure, which are distributed in a staggered manner along the thickness direction of the semiconductor substrate. And, in at least five kinds of gate-all-around transistors, the different channel regions belonging to at least two kinds of gate-all-around transistors include the same material of the portion of the nano structure, and the portion of the nano structure included in the different channel regions are aligned along the thickness direction of the semiconductor substrate, based on this, when the semiconductor device provided by the invention is manufactured, at least three semiconductor layers which are different in material and are alternately laminated can be formed on the semiconductor substrate, and at least three semiconductor layers which are alternately stacked are mutually channel layers/sacrificial layers, so that the at least five types of gate-all-around transistors are manufactured, and the channel regions with different conductive characteristics can be obtained by selecting different semiconductor layers and combining different semiconductor layers in the channel regions of part of the gate-all-around transistors, thereby realizing that the gate-all-around transistors with different absolute values have different threshold voltages. Meanwhile, different kinds of gate-all-around transistors with different absolute values and different threshold voltages are obtained by forming gate stack structures with different thicknesses and/or materials without adopting a complex deposition-etching-deposition mode, so that the manufacturing pro