CN-119808670-B - High-reliability circuit low-power consumption design method

CN119808670BCN 119808670 BCN119808670 BCN 119808670BCN-119808670-B

Abstract

The invention discloses a low-power consumption design method of a digital integrated circuit, which realizes the low-power consumption design target of the digital integrated circuit by adjusting the probability of an input signal of the digital integrated circuit. And according to the power supply voltage of the digital integrated circuit and the probability of the input signal, the two have combined effect on the aging delay of the digital integrated circuit, so that the low-power-consumption design target of the digital integrated circuit is realized. The design method comprises the steps of establishing an input signal probability propagation model of a critical path of the digital integrated circuit, and measuring and calculating the input signal probability of each logic gate standard unit on the critical path. And constructing an aging delay prediction model of the digital integrated circuit, and predicting the aging delay of the digital integrated circuit according to the probability of the input signals of the standard units on the critical path.

Inventors

REN PENGPENG
JI ZHIGANG
Sun Eqi

Assignees

上海交通大学

Dates

Publication Date: 20260512
Application Date: 20241219

Claims (5)

1. A design method for low power consumption of digital integrated circuit is characterized by that the aging delay frame affected by power supply voltage and input signal probability is built, the input signal probability propagation model of key path of said digital integrated circuit is built for measuring and calculating the input signal probability of each logic gate standard unit on said key path, Constructing an aging delay prediction model of the digital integrated circuit, predicting the aging delay of the digital integrated circuit according to the probability of the input signal of the standard cell on the critical path, On the premise of keeping the initial calculation speed index of the digital integrated circuit unchanged, in the overlapped area, the aging delay of the circuit running at lower voltage is kept consistent with the aging delay of the circuit running at higher voltage by adjusting the probability of the input signal, the low-power consumption design goal of the digital integrated circuit is realized without sacrificing the calculation capacity, Wherein the overlapping region refers to an overlapping portion shown by a fluctuation range of the aging delay corresponding to the adjacent voltage in a curve segment where the response of the aging delay to the voltage change is weak, And simultaneously, the sensitivity of the critical path is enhanced to enlarge the overlapping area of the aging delay curves of the digital integrated circuit under different power supply voltages, so that the power supply voltage adjustment space is enlarged.
2. The design method according to claim 1, further comprising the steps of, in constructing the aging delay prediction model: Analyzing the timing report file and netlist file synthetically generated by the digital integrated circuit, Extracting critical paths and data transmission relations between the input ends of all standard units and the input ends of the digital integrated circuit under preset voltage after aging, The probability of the input signal of each standard cell on the critical path is calculated by establishing standard cell input-output signal probability transmission logic.
3. The design method of claim 1, wherein the method of enhancing the sensitivity of the critical path includes analyzing the effect of signal probabilities of different bits on the aging delay of each standard cell on the critical path, and determining the bit in which at least 2 effects are most effective.
4. A design method according to claim 3, wherein the method of enhancing the sensitivity of the critical path further comprises discarding the bit having the least influence on the accuracy from among the two bits having the greatest influence on the circuit degradation delay when the influence ranges of the two bits having the greatest influence on the circuit degradation delay overlap.
5. A digital integrated circuit, characterized in that the digital integrated circuit is designed by the digital integrated circuit low power consumption design method as claimed in any one of claims 1 to 4.

Description

High-reliability circuit low-power consumption design method Technical Field The present invention relates to the field of semiconductor device reliability and integrated circuit design, and more particularly, to a method for designing a highly reliable circuit with low power consumption, and a digital integrated circuit designed by the method. Background In the area of integrated circuit design and semiconductor device reliability issues, low power consumption designs have become the most recently focused technical goal, including the issue of how to reduce dynamic and static power consumption of circuits. For solving this problem, voltage scaling has been considered as an effective method of operating a circuit with as low a voltage as possible while ensuring performance, thereby reducing power consumption. In addition, the dynamic voltage and frequency adjustment technology balances performance and power consumption by adjusting voltage and frequency, and the energy consumption efficiency of the circuit is remarkably improved. However, voltage scaling requires a fine control and delicate balance to avoid accelerated circuit aging, which may reduce the reliability of the system over time. Thus, in implementing these low power consumption techniques, their impact on long term stability needs to be carefully considered. In the aspect of low-power design of integrated circuits, clock gating is another adopted method. It reduces dynamic power consumption by disabling the clock signal of inactive circuit components. This approach has proven to be effective in reducing unnecessary switching activity and thus power consumption. On the other hand, the gating method for the power supply circuit reduces the static power consumption by completely turning off the power supply of the inactive circuit block. This approach is particularly effective in minimizing leakage power during idle, helping to save overall power consumption of the systolic array. In practical applications, the design and implementation of clock gating also requires consideration of a number of factors, including timing, power consumption, area, and design complexity. For example, the designer needs to decide when and how to introduce clock gating in the design, and how to balance the effects of the number of gating cells and power savings. Furthermore, approximation calculation techniques are employed in circuits to have become a promising strategy for improving energy consumption efficiency, especially in applications requiring a trade-off between computational accuracy and power consumption. Approximation (Approximate Computing, AC) is a technique used in circuit design to improve energy consumption efficiency. It significantly reduces the power consumption of the circuit by allowing a degree of controlled loss of accuracy. This technique is particularly useful in applications where a certain degree of error can be tolerated, such as in the fields of machine learning, image processing, signal processing, etc. The principle of approximate calculation is to intentionally introduce acceptable errors in the calculation process, so as to reduce the use of calculation resources and reduce the energy consumption. For example, in digital circuits, approximate computation is achieved by simplifying the computation logic, reducing the data accuracy, or reducing the computation steps, reducing the amount of computation and power consumption without significantly affecting the final result. Disclosure of Invention In one embodiment of the disclosure, a method for designing a high-reliability digital integrated circuit with low power consumption, which realizes the design with low power consumption by adjusting the probability of an input signal, comprises, By establishing a new frame of aging delay which is jointly influenced by the power supply voltage and the probability of an input signal, a method capable of reducing the voltage by about 10% and keeping the same calculation speed after the circuit is aged is introduced, so that the energy efficiency is remarkably improved; constructing a critical path signal probability propagation model, and precisely calculating the signal probability at a critical path unit according to the input signal probability by carefully analyzing the netlist; Two strategies have been proposed to enhance the sensitivity of the path to signal probability variations, thereby expanding the voltage regulation space and improving the effectiveness of the inventive method. The calculation speed of the circuit can be kept unchanged while the working voltage is reduced by adjusting the signal input probability. One of the beneficial effects of the embodiments of the present disclosure is to realize a low power circuit design by changing the probability of an input signal. Drawings The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the