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CN-119834060-B - Vertical cavity surface emitting laser and preparation method thereof

CN119834060BCN 119834060 BCN119834060 BCN 119834060BCN-119834060-B

Abstract

The invention relates to the technical field of semiconductors, in particular to a vertical cavity surface emitting laser and a preparation method thereof, wherein the laser comprises an n-face electrode layer, a substrate layer, a buffer layer and an n-DBR layer which are sequentially arranged from bottom to top, an SiO 2 insulating layer positioned on the periphery is arranged above the n-DBR layer, and an n-lower oxidation limiting structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation limiting structure layer, a p-DBR layer, a contact layer and a p-face electrode layer which form a cylindrical platform are sequentially arranged in the center of the SiO 2 insulating layer from bottom to top. The invention adopts the symmetrical oxidation limiting structure to limit more carriers in the oxidation holes, thereby improving the output power and the electro-optical conversion efficiency, and regulating and controlling the number and the distribution of transverse modes.

Inventors

  • JIA ZHIGANG
  • Jia Xiuyang
  • CHEN XIAODONG
  • DONG HAILIANG
  • LIANG JIAN
  • XU BINGSHE

Assignees

  • 太原理工大学
  • 山西浙大新材料与化工研究院

Dates

Publication Date
20260508
Application Date
20241220

Claims (9)

  1. 1. The vertical cavity surface emitting laser is characterized by comprising an n-face electrode layer, a substrate layer, a buffer layer and an n-DBR layer which are sequentially arranged from bottom to top, wherein an SiO 2 insulating layer positioned at the periphery is arranged above the n-DBR layer, and the center of the SiO 2 insulating layer is sequentially provided with an n-lower oxidation limiting structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation limiting structure layer, a p-DBR layer, a contact layer and a p-face electrode layer which form a cylindrical platform from bottom to top; The n-lower oxidation limiting structure layer comprises an n-lower oxidation limiting structure with at least one period, wherein the n-lower oxidation limiting structure is provided with an n-Al z1 GaAs high refractive index layer, an n-Al 0.98 GaAs oxidation limiting layer and an n-Al 0.9 GaAs low refractive index layer sequentially from bottom to top, and a first aluminum oxide layer is formed on the periphery of the n-Al 0.98 GaAs oxidation limiting layer through a wet oxidation process; The p-upper oxidation limiting structure layer comprises at least one period of p-upper oxidation limiting structure, the p-upper oxidation limiting structure comprises a p-Al 0.9 GaAs low refractive index layer, a p-Al 0.98 GaAs oxidation limiting layer and a p-Al z2 GaAs high refractive index layer which are sequentially arranged from bottom to top, a second aluminum oxide layer is formed on the periphery of the p-Al 0.98 GaAs oxidation limiting layer through a wet oxidation process, z1 and z2 respectively represent Al components in corresponding materials, and z1=z2=0.05.
  2. 2. The vcsels of claim 1, wherein the n-Al 0.98 GaAs oxidation confinement layer has a thickness of 30nm and the p-Al 0.98 GaAs oxidation confinement layer has a thickness of 30nm.
  3. 3. The vertical cavity surface emitting laser according to claim 1, wherein said n-Al 0.98 GaAs oxidation confinement layer has a doping concentration of 1X 10 18 cm -3 doped with Si, and said p-Al 0.98 GaAs oxidation confinement layer has a doping concentration of 1X 10 18 cm -3 doped with C.
  4. 4. The vertical cavity surface emitting laser according to claim 1, wherein an n-AlGaAs transition layer is further provided between the n-Al z1 GaAs high refractive index layer and the n-Al 0.98 GaAs oxidation confinement layer, and the Al composition thereof is linearly graded from z1 to 0.9; A p-AlGaAs transition layer is further arranged between the p-Al 0.98 GaAs oxidation limiting layer and the p-Al z2 GaAs high-refractive-index layer, and the Al component of the p-AlGaAs transition layer is gradually changed from 0.9 to z2 linearly.
  5. 5. The vertical cavity surface emitting laser according to claim 1, wherein said n-side electrode layer comprises gold and nickel layers arranged in sequence from bottom to top; The substrate layer is an n-GaAs substrate, the thickness is 120 mu m, the doping concentration is 2 multiplied by 10 18 cm -3 , and Si is doped; The buffer layer is an n-GaAs buffer layer, the thickness is 150 nm, the doping concentration is 2 multiplied by 10 18 cm -3 , and Si is doped; the lower space layer is an AlGaAs lower space layer, the thickness is 114.1 nm, and the doping is avoided; The upper space layer is an AlGaAs upper space layer, and the thickness is 114.1 nm; The contact layer is a p-GaAs contact layer, the thickness is 100 nm, the doping concentration is 2 multiplied by 10 19 cm -3 , and C is doped; the p-surface electrode layer comprises titanium, platinum and gold layers which are sequentially arranged from bottom to top.
  6. 6. The vertical cavity surface emitting laser according to claim 1, wherein said p-side electrode layer has a circular shape with a center coinciding with a center of said n-lower oxidation-limiting structure layer, and an inner diameter larger than radii of said n-Al 0.98 GaAs oxidation-limiting layer and said p-Al 0.98 GaAs oxidation-limiting layer.
  7. 7. The vertical cavity surface emitting laser according to claim 1, wherein the n-DBR layer is formed by periodically overlapping 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al 0.9 GaAs low refractive index layer, wherein the thickness of the n-Al z3 GaAs high refractive index layer is λ/4n H1 -20 nm, z3 satisfies 1.424+1.247z3> 1240/(λ -50), the thickness of the n-Al 0.9 GaAs low refractive index layer is λ/4n L1 -20 nm, λ is the emission wavelength of the VCSEL, n H1 is the refractive index of the n-Al z3 GaAs high refractive index layer, and n L1 is the refractive index of the n-Al 0.9 GaAs low refractive index layer; A 20-nm n-AlGaAs transition layer is arranged on each n-Al z3 GaAs high refractive index layer, and the Al component in the transition layer is linearly graded from z3 to 0.9; The p-DBR layer is formed by periodically overlapping 23 pairs of p-Al 0.9 GaAs low-refractive-index layers and p-Al z4 GaAs high-refractive-index layers, wherein the thickness of the p-Al z4 GaAs high-refractive-index layers is lambda/4 n H2 -20 nm, z4 satisfies 1.424+1.247z4> 1240/(lambda-50), the thickness of the p-Al 0.9 GaAs low-refractive-index layers is lambda/4 n L2 -20 nm, lambda is the emission wavelength of the VCSEL, n H2 is the refractive index of the n-Al z4 GaAs high-refractive-index layers, and n L2 is the refractive index of the n-Al 0.9 GaAs low-refractive-index layers; A20-nm AlGaAs transition layer is arranged on each p-Al z4 GaAs high-refractive-index layer, the Al component is linearly graded from z4 to 0.9, a 20-nm p-AlGaAs transition layer is arranged on each p-Al 0.9 GaAs low-refractive-index layer, the Al component is linearly graded from 0.9 to z4, a 30-nm p-AlGaAs transition layer is arranged on the uppermost p-Al z4 GaAs high-refractive-index layer, the Al component is linearly graded from z4 to 0, the doping concentration is linearly graded from 3× 18 cm -3 to 2× 19 cm -3 , and z3 and z4 respectively represent the Al component in corresponding materials.
  8. 8. A vertical cavity surface emitting laser according to claim 7, wherein z3=z4.
  9. 9. The method for manufacturing the vertical cavity surface emitting laser according to any one of claims 1 to 8, comprising an epitaxial growth step and a chip process step, wherein the epitaxial growth step adopts a metal organic chemical vapor deposition technology for epitaxial growth, and comprises the following steps: Step 1, selecting a (001) plane n-type GaAs substrate, and placing the n-type GaAs substrate on a graphite tray in an MOCVD reaction cavity; step 2, introducing arsine (AsH 3 ) in a hydrogen atmosphere, raising the temperature of the graphite tray to 680 ℃ under the protection of AsH 3 , and baking at a high temperature to remove impurities and oxide layers on the surface of the substrate; Step 3, reducing the temperature to 640 ℃, introducing trimethylgallium (TMGa) and silane (SiH 4 ), controlling the growth rate of the GaAs buffer layer by regulating and controlling the flow of TMGa, controlling the V/III ratio to be 60 by regulating and controlling the flow of AsH 3 , controlling the doping concentration by regulating and controlling the flow of SiH 4 , and growing the n-GaAs buffer layer; Step 4, keeping the growth temperature at 640 ℃, the V/III ratio at 60, introducing Trimethylaluminum (TMAL), and gradually changing the flow rate from 0 to the flow rate required by Al z3 GaAs growth so as to form an AlGaAs transition layer on the n-GaAs buffer layer; Step 5, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, and regulating the flow of SiH 4 to enable the doping concentration to be 2 multiplied by 10 18 cm -3 , and growing an Al z3 GaAs high refractive index layer in the n-DBR; Step 6, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, and linearly gradually changing the flow rates of TMGa and TMAl to the flow rate required by Al 0.9 GaAs growth to form an AlGaAs transition layer on the Al z3 GaAs high-refractive-index layer; step 7, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, and regulating the flow of SiH 4 to enable the doping concentration to be 2 multiplied by 10 18 cm -3 , and growing an Al 0.9 GaAs low refractive index layer in the n-DBR; step 8, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, and linearly gradually changing the flow rates of TMGa and TMAl to the flow rate required by Al z3 GaAs growth to form an AlGaAs transition layer on the Al 0.9 GaAs low refractive index layer; Step 9, circularly repeating the steps 5-8 to form 40 pairs of n-DBRs with doping concentration of 2X 10 18 cm -3 ; Step 10, regulating the flow of SiH 4 to make the doping concentration be 1 multiplied by 10 18 cm -3 , and repeating the steps 5 to 8 again to form 3 pairs of n-DBRs with the doping concentration of 1 multiplied by 10 18 cm -3 ; step 11, adopting the growth parameters in the step 5, but shortening the growth time, and growing an n-Al z1 GaAs high-refractive index layer in the n-lower oxidation limiting structure; step 12, repeating the step 6 to form an AlGaAs transition layer on the n-Al z1 GaAs high refractive index layer; Step 13, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, switching the TMGa and TMAl flow to the flow required by Al 0.98 GaAs growth, regulating SiH 4 flow to enable the doping concentration to be 1X 10 18 cm -3 , and growing an n-Al 0.98 GaAs lower oxidation limiting layer 05 in an n-lower oxidation limiting structure 04; Step 14, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, switching the TMGa and TMAl flow to the flow required by Al 0.9 GaAs growth, regulating SiH 4 flow to enable the doping concentration to be 1X 10 18 cm -3 , and growing an n-Al 0.9 GaAs low refractive index layer in an n-lower oxidation limiting structure; step 15, keeping the growth temperature at 640 ℃, the V/III ratio at 60, cutting off SiH 4 supply, linearly gradually changing the flow of TMGa and TMAl to the flow required by the growth of the AlGaAs quantum barrier layer, and growing an AlGaAs lower space layer; step 16, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, and the flow rates of TMGa and TMAL are unchanged, growing an AlGaAs quantum barrier layer, cutting off TMGa and TMAL sources after the growth is completed, and suspending the growth for 5s; Step 17, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, introducing TMGa, TMAL and TMIn sources, regulating and controlling the flow of the TMGa, TMAL and TMIn sources to enable the growth rate of the InGaAlAs quantum well layer to be 0.2nm/s, growing the quantum well layer, cutting off the TMGa, TMAL and TMIn sources after the growth is completed, and suspending the growth for 5s; step 18, repeating the steps 16-17 for a plurality of cycles to form a quantum well active region; step 19, repeating the step 16 to finish the last AlGaAs quantum barrier layer of the quantum well active region; Step 20, maintaining the growth temperature at 640 ℃, the V/III ratio at 60, introducing TMGa and TMAL sources, setting the initial flow as the flow required by the growth of the AlGaAs quantum barrier layer, and then linearly gradually changing to the flow required by the growth of Al 0.9 GaAs to form an AlGaAs upper space layer; Step 21, maintaining the growth temperature at 640 ℃, regulating the V/III ratio to 40, keeping the flow rates of TMGa and TMAl unchanged, introducing carbon tetrabromide as a C doping source, regulating the flow rate of the carbon tetrabromide to enable the doping concentration to be 1X 10 18 cm -3 , and growing a p-Al 0.9 GaAs low refractive index layer in a p-upper oxidation limiting structure; Step 22, maintaining the growth temperature at 640 ℃, the V/III ratio at 40, switching the TMGa and TMAl flow to the flow required by Al 0.98 GaAs growth, and growing a p-Al 0.98 GaAs oxidation limiting layer in a p-upper oxidation limiting structure by regulating the carbon tetrabromide flow to enable the doping concentration to be 1X10 18 cm -3 ; Step 23, maintaining the growth temperature at 640 ℃, switching the initial flow of TMGa and TMAL to the flow required by Al 0.9 GaAs growth at the V/III ratio of 40, and then linearly gradually changing to the flow required by Al z2 GaAs growth to grow an AlGaAs transition layer of 20 nm; step 24, maintaining the growth temperature at 640 ℃, the V/III ratio at 40, and the TMGa and TMAl flow unchanged, and growing a p-Al z2 GaAs high refractive index layer in a p-upper oxidation limiting structure by regulating and controlling the CBr 4 flow to enable the doping concentration to be 1X 10 18 cm -3 ; Step 25, maintaining the growth temperature at 640 ℃, the V/III ratio at 40, and linearly gradually changing the flow rates of TMGa and TMAL to the flow rate required by Al 0.9 GaAs growth to form an AlGaAs transition layer of 20 nm; Step 26, maintaining the growth temperature at 640 ℃, the V/III ratio at 40, and regulating and controlling the flow of CBr 4 to enable the doping concentration to be 1 multiplied by 10 18 cm -3 , and growing a p-Al 0.9 GaAs low refractive index layer in the p-DBR; Step 27, maintaining the growth temperature at 640 ℃, the V/III ratio at 40, and linearly gradually changing the flow rates of TMGa and TMAL to the flow rate required by Al z4 GaAs growth to form an AlGaAs transition layer of 20 nm; Step 28, maintaining the growth temperature at 640 ℃, the V/III ratio at 40, and regulating and controlling the flow of CBr 4 to enable the doping concentration to be 1 multiplied by 10 18 cm -3 , and growing a p-Al z4 GaAs high refractive index layer in the p-DBR; step 29, circularly repeating the steps 25-28 to form 3 pairs of p-DBRs with doping concentration of 1X 10 18 cm -3 ; Step 30, regulating the flow of CBr 4 to enable the doping concentration to be 3 multiplied by 10 18 cm -3 , circularly repeating the steps 25-28 to form 20 pairs of p-DBRs with the doping concentration of 3 multiplied by 10 18 cm -3 , and completing the growth of the p-DBRs 09; Step 31, the growth temperature is linearly reduced to 580 ℃ from 640 ℃, the flow of TMAl is linearly graded to 0, the V/III ratio is linearly graded to 30, the flow of CBr 4 is linearly graded to the flow required by doping of the p+ GaAs contact layer, an AlGaAs transition layer from the p-DBR to the p+ GaAs contact layer is formed, the Al component is linearly graded to 0 from z4, and the doping concentration is linearly graded to 2X 10 19 cm -3 from 3X 10 18 cm -3 ; step 32, keeping the growth temperature at 580 ℃ and the V/III ratio at 30, cutting off TMAL, TMGa and CBr 4 flow, and growing a p+ GaAs contact layer; Step 33, cutting off TMGa and CBr 4 , naturally cooling to normal temperature, and then cutting off AsH 3 to complete epitaxial wafer growth; The chip process steps comprise: Step 34, cleaning the epitaxial wafer by adopting a standard epitaxial wafer cleaning process; step 35, forming an electrode pattern of the p-side electrode layer by adopting a photoetching and developing process, reserving photoresist outside an electrode area of the p-side electrode layer, and removing the photoresist in the electrode area of the p-side electrode layer; step 36, adopting an electron beam evaporation or magnetron sputtering process to deposit a metal layer corresponding to the p-side electrode; Step 37, stripping metal outside the glass annular electrode by using a tape adhesive to leave metal in the annular electrode area to form a p-surface annular electrode; Step 38, forming a pattern of a cylindrical table on the surface of the wafer by adopting a photoetching and developing process, leaving photoresist in the area of the cylindrical table, and removing the photoresist outside the cylindrical table; step 39, etching a cylindrical table top by adopting a dry etching process until the n-DBR layer is etched, and then removing photoresist on the cylindrical table top; step 40, adopting a chemical polishing process to treat the side wall of the cylindrical table top, and eliminating etching damage of the side wall; step 41, oxidizing the oxidation limiting layers in the n-lower oxidation limiting structure layer and the p-upper oxidation limiting structure layer by adopting a wet oxidation process to form an alumina layer at the periphery of the oxidation limiting layers; Step 42, adopting a plasma chemical vapor deposition technology to deposit a SiO 2 insulating layer, wherein the thickness of the SiO 2 insulating layer is larger than the height of the cylinder table so as to protect the side wall of the cylinder table; Step 43, performing alignment on the cylindrical table by adopting a photoetching and developing process, removing photoresist on the upper surface of the cylindrical table, and reserving the photoresist outside the cylindrical table area to protect the SiO 2 insulating layer; Step 44, removing the SiO 2 insulating layer on the upper surface of the cylinder table by adopting a wet etching process, leaking out the p-surface annular electrode, and then removing all photoresist; 45, forming a lead wire and a Pad pattern of the p-side electrode layer by adopting a photoetching and developing process; step 46, adopting an electron beam evaporation or magnetron sputtering process to deposit p-side metal; step 47, stripping photoresist on the surface of the wafer and metal on the photoresist by adopting a stripping process with glue to form a p-surface electrode lead and a Pad; Step 48, thinning the n-GaAs substrate to 120 mu m by adopting a grinding process; Step 49, polishing the back surface of the n-GaAs substrate by adopting a polishing process; step 50, depositing metal on the back of the n-GaAs substrate by adopting an electron beam evaporation or magnetron sputtering process to form an n-face electrode; Step 51, alloying the n-side electrode and the p-side electrode by adopting a high-temperature annealing process to form ohmic contact with the semiconductor; And 52, scribing and splitting to form a single tube or an array chip, and finishing the preparation of the GaAs-based VCSEL chip.

Description

Vertical cavity surface emitting laser and preparation method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a vertical cavity surface emitting laser and a preparation method thereof, which improve the photoelectric performance of the vertical cavity surface emitting laser through a symmetrical oxidation limiting structure. Background A vertical cavity Surface emitting laser (VERTICAL CAVITY Surface EMITTING LASER, VCSEL) is a semiconductor laser that emits laser light perpendicular to the Surface of the device. Due to the special chip structure, the VCSEL has the advantages of low threshold value, low power consumption, easiness in coupling of single longitudinal mode and circular light spots with optical fibers, capability of on-chip testing, easiness in array, low manufacturing cost and the like. The method is widely applied to the fields of intelligent sensing, optical interconnection, optical communication, optical storage, quantum precision measurement and the like. The VCSEL was first proposed by japanese scientist Iga in 1977, and after thirty years of development, the VCSEL has been commercialized on a large scale and device types such as GaAs-based VCSEL, inP-based VCSEL, antimonide VCSEL, gaN-based VCSEL, etc. are formed. The GaAs-based VCSEL is the VCSEL product which is most mature in development and most widely applied in commercialization, and mainly has two points, namely (1) the AlGaAs material is naturally lattice matched with the GaAs substrate, the refractive index difference is large, a distributed Bragg reflector (Distributed Bragg Reflector, DBR) structure with high reflectivity and low defect density can be easily grown, and (2) the AlGaAs material with high Al component can form an oxidation limiting structure through a wet oxidation process, so that the AlGaAs material has remarkable effect on reducing the loss of VCSEL devices, and is a key technology for promoting the industrialization of the GaAs-based VCSEL. Thanks to the research of AlGaAs materials in deep systems, the wet oxidation process of GaAs-based VCSELs is now very mature, and therefore the oxidation-limiting structure has become the most widely used current limiting and optical field limiting method. GaAs-based VCSELs typically have an oxide confinement layer disposed between a first pair of P-DBRs adjacent to the active region that is capable of confining the diffusion of carriers and optical fields, confining most of the carriers and photons within the oxide aperture, but still having a significant amount of carriers and photons diffuse out of the oxide aperture and not forming efficient stimulated radiation. Researchers have also provided double oxide confinement layers in the P-DBR to reduce parasitic capacitance of the VCSEL and improve modulation bandwidth, but this structure lacks current confinement on the N-side and has lower output power and electro-optical conversion efficiency. Disclosure of Invention The invention aims to solve the technical problems that (1) the GaAs-based VCSEL adopting a p-type single-oxidation limiting layer structure has no current limit on the n side, has serious electron diffusion, (2) the limiting capacity on carriers is weak, is unfavorable for improving the carrier injection efficiency, and (3) the limiting effect on an optical field is poor, particularly, a high-order transverse mode is often out of an oxidation hole, and cannot form effective mode gain, so that the output power is reduced. In order to solve the technical problems, the vertical cavity surface emitting laser comprises an n-surface electrode layer, a substrate layer, a buffer layer and an n-DBR layer which are sequentially arranged from bottom to top, wherein an SiO 2 insulating layer positioned at the periphery is arranged above the n-DBR layer, and the center of the SiO 2 insulating layer is sequentially provided with an n-lower oxidation limiting structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation limiting structure layer, a p-DBR layer, a contact layer and a p-surface electrode layer which form a cylindrical platform from bottom to top; The n-lower oxidation limiting structure layer comprises an n-lower oxidation limiting structure with at least one period, wherein the n-lower oxidation limiting structure is provided with an n-Al z1 GaAs high refractive index layer, an n-Al 0.98 GaAs oxidation limiting layer and an n-Al 0.9 GaAs low refractive index layer sequentially from bottom to top, and a first aluminum oxide layer is formed on the periphery of the n-Al 0.98 GaAs oxidation limiting layer through a wet oxidation process; The p-upper oxidation limiting structure layer comprises a p-upper oxidation limiting structure with at least one period, the p-upper oxidation limiting structure comprises a p-Al 0.9 GaAs low refractive index layer, a p-Al 0.98 GaAs oxidation limiting layer and a p-Al z2 G