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CN-119851701-B - Voltage holding circuit and system on chip

CN119851701BCN 119851701 BCN119851701 BCN 119851701BCN-119851701-B

Abstract

The invention provides a voltage holding circuit and a system on chip, wherein the voltage holding circuit comprises a charge pump, a trigger unit, a first switch unit and a voltage holding unit, the trigger unit is respectively connected with the control ends of the charge pump and the first switch unit, the first end of the first switch unit is connected with the output end of the charge pump, the second end of the first switch unit is connected with the voltage holding unit, and the voltage holding unit is also used for being connected with a DNW array of a memory. The voltage of the input end of the voltage holding unit is in a first target voltage interval by controlling the charge pump to work or rest, so that the voltage of the parasitic capacitance of the DNW array is kept in a second target voltage interval. When the read-write operation of the memory is required, the power supply voltage of the electronic equipment can quickly raise the memory to the working voltage, so that the read-write operation of the memory can be responded quickly, and the low power consumption in the standby mode is ensured.

Inventors

  • ZHU ZEYU

Assignees

  • 普冉半导体(上海)股份有限公司

Dates

Publication Date
20260508
Application Date
20241225

Claims (8)

  1. 1. A voltage holding circuit, characterized in that the voltage holding circuit comprises a charge pump, a trigger unit, a first switch unit and a voltage holding unit; the triggering unit is respectively connected with the charge pump and the control end of the first switch unit; A first end of the first switch unit is connected with the output end of the charge pump, and a second end of the first switch unit is connected with the voltage holding unit; The voltage holding unit is also used for connecting a DNW array of the memory; the voltage holding unit comprises a first capacitor and an NMOS tube; A wiring terminal is led out of the connection part of one pole of the first capacitor and the grid electrode of the NMOS tube and is used as the input end of the voltage holding unit and connected with the second end of the first switch unit; The other electrode of the first capacitor is grounded, the drain electrode of the NMOS tube is connected to the output end of the charge pump, and the source electrode of the NMOS tube is connected to the DNW array; the voltage holding circuit further comprises a first resistor, a second resistor and a second switch unit; One end of the first resistor is connected to the second end of the first switch unit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded; One end of the second switch unit is connected with a wiring terminal led out between the first resistor and the second resistor, and the other end of the second switch unit is connected with the input end of the voltage holding unit; the triggering unit is connected with the control end of the second switching unit and is used for controlling the state of the second switching unit and the state of the first switching unit to be consistent.
  2. 2. The voltage holding circuit according to claim 1, wherein, The triggering unit is used for sending a starting signal to the charge pump under the condition that a first triggering condition is met, and controlling the first switch unit to be switched to a closed state so as to enable the charge pump to charge the voltage holding unit, and keeping the voltage of the input end of the voltage holding unit within a first target voltage interval; the triggering unit is used for sending a rest signal to the charge pump and controlling the first switching unit to be switched into an off state under the condition that a second triggering condition is met; The voltage holding unit is used for charging the DNW array so as to enable the voltage of the parasitic capacitance of the DNW array to be kept within a second target voltage interval.
  3. 3. The voltage holding circuit according to claim 2, wherein, The first trigger condition being met indicates that the input end voltage of the voltage holding unit is reduced to a third voltage threshold, and the third voltage threshold is the lower limit of the first target voltage interval; The second trigger condition is met, which means that the voltage of the input end of the voltage holding unit rises to a fourth voltage threshold, and the fourth voltage threshold is the upper limit of the first target voltage interval.
  4. 4. The voltage holding circuit according to claim 2, wherein, The triggering unit is used for detecting the current voltage of the output end of the charge pump; the triggering unit is used for determining that the first triggering condition is met under the condition that the current voltage is lower than a first voltage threshold value; And the triggering unit is used for determining that the second triggering condition is met when the current voltage reaches a second voltage threshold value.
  5. 5. The voltage holding circuit according to claim 2, wherein, The triggering unit is used for recording the starting interval duration of the charge pump, and determining that the first triggering condition is met when the starting interval duration is equal to a first time threshold; the triggering unit is used for recording the continuous starting time length of the charge pump, and determining that the second triggering condition is met when the continuous starting time length is equal to a second time threshold value; the starting interval duration represents a duration from a time when the charge pump last enters a rest state to a current time, and the continuous starting duration represents a duration from a time when the charge pump last enters a starting state to a current time.
  6. 6. The voltage holding circuit according to claim 1, wherein the voltage holding unit further includes a third switching unit; The first end of the third switch unit is connected to the output end of the charge pump, and the second end of the third switch unit is connected to the drain electrode of the NMOS tube.
  7. 7. The voltage holding circuit according to claim 6, wherein the third switching unit is in a closed state when an electronic device in which the voltage holding circuit is disposed is in a standby mode; when the electronic equipment is in a working mode, the third switch unit is in an off state.
  8. 8. A system on chip, characterized in that the system on chip comprises a memory and a voltage holding circuit according to any of claims 1-7.

Description

Voltage holding circuit and system on chip Technical Field The present invention relates to the field of electronic devices, and in particular, to a voltage holding circuit and a system on a chip. Background In Standby Mode (also known as SLEEP Mode or Standby Mode), the electronic device reduces power consumption to extend the Standby period of the battery. FLASH memory (FLASH memory) is generally provided in electronic devices, and may not normally perform read and write operations at lower voltages due to the operating characteristics of FLASH memory. When data needs to be read from the flash memory, the electronic device is switched to a read mode in order to ensure the reliability of data access, and the power supply is sufficient to support the read operation of the flash memory. Due to the characteristics of flash memory, when an electronic device is switched from a standby mode to a read mode, particularly when the flash memory requires a voltage higher than the normal operating voltage VDD to perform an operation, maintaining a sufficient voltage supply increases power consumption, which conflicts with the goal of saving energy in the standby mode. Disclosure of Invention The present invention is directed to a voltage holding circuit and a system on a chip to improve the above-mentioned problems. In order to achieve the above object, the technical scheme adopted by the embodiment of the invention is as follows: in a first aspect, an embodiment of the present invention provides a voltage holding circuit, including a charge pump, a trigger unit, a first switch unit, and a voltage holding unit; the triggering unit is respectively connected with the charge pump and the control end of the first switch unit; A first end of the first switch unit is connected with the output end of the charge pump, and a second end of the first switch unit is connected with the voltage holding unit; the voltage holding unit is also used for connecting with a DNW array of the memory. Optionally, the trigger unit is configured to send a start signal to the charge pump and control the first switch unit to switch to a closed state when a first trigger condition is met, so that the charge pump charges the voltage holding unit, and the input terminal voltage of the voltage holding unit is kept within a first target voltage interval; the triggering unit is used for sending a rest signal to the charge pump and controlling the first switching unit to be switched into an off state under the condition that a second triggering condition is met; The voltage holding unit is used for charging the DNW array so as to enable the voltage of the parasitic capacitance of the DNW array to be kept within a second target voltage interval. Optionally, the triggering unit is configured to detect a current voltage of an output terminal of the charge pump; the triggering unit is used for determining that the first triggering condition is met under the condition that the current voltage is lower than a first voltage threshold value; And the triggering unit is used for determining that the second triggering condition is met when the current voltage reaches a second voltage threshold value. Optionally, the triggering unit is configured to record a start interval duration of the charge pump, and determine that the first triggering condition is met when the start interval duration is equal to a first time threshold; the triggering unit is used for recording the continuous starting time length of the charge pump, and determining that the second triggering condition is met when the continuous starting time length is equal to a second time threshold value; the starting interval duration represents a duration from a time when the charge pump last enters a rest state to a current time, and the continuous starting duration represents a duration from a time when the charge pump last enters a starting state to a current time. Optionally, the voltage holding unit includes a first capacitor and an NMOS transistor; A wiring terminal is led out of the connection part of one pole of the first capacitor and the grid electrode of the NMOS tube and is used as the input end of the voltage holding unit and connected with the second end of the first switch unit; The other electrode of the first capacitor is grounded, the drain electrode of the NMOS tube is connected to the output end of the charge pump, and the source electrode of the NMOS tube is connected to the DNW array. Optionally, the voltage holding circuit further includes a first resistor, a second resistor, and a second switching unit; One end of the first resistor is connected to the second end of the first switch unit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded; One end of the second switch unit is connected with a wiring terminal led out between the first resistor and the second resistor, and the other end of the secon