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CN-119922948-B - MOSFET device and chip

CN119922948BCN 119922948 BCN119922948 BCN 119922948BCN-119922948-B

Abstract

The embodiment of the invention provides a MOSFET device and a chip, which comprise an N-type substrate, an N-type epitaxial layer, an N-type current expansion layer, a first P-type buried layer, a first N+ region, a groove, a source electrode polycrystalline silicon region, a grid electrode polycrystalline silicon region and an oxide layer, wherein the N-type epitaxial layer is arranged on the other side of the N-type substrate, the N-type current expansion layer and the first P-type buried layer are arranged above the N-type epitaxial layer, the N-type current expansion layer is connected with the first P-type buried layer, the first N+ region is arranged in the groove formed on the surface of the first P-type buried layer, the groove is formed above the N-type current expansion layer and the first P-type buried layer, the source electrode polycrystalline silicon region, the grid electrode polycrystalline silicon region and the oxide layer are arranged in the groove, and the oxide layer covers the surfaces of the source electrode polycrystalline silicon region and the grid electrode polycrystalline silicon region. According to the embodiment of the invention, the channel diode is formed below the source polycrystalline silicon through the N-type current expansion layer and the first P-type buried layer, and is conducted earlier than the body diode when the device is in a reverse conduction state, so that the problems of large follow current loss and bipolar degradation of the body diode when the device is in a reverse follow current working mode are avoided.

Inventors

  • CHEN HAOYU

Assignees

  • 珠海格力电器股份有限公司

Dates

Publication Date
20260508
Application Date
20241225

Claims (10)

  1. 1. A MOSFET device, the device comprising: An N-type substrate; the N-type epitaxial layer is arranged on one side of the N-type substrate; The N-type current expansion layer and the first P-type buried layer are arranged above the N-type epitaxial layer; the N-type current expansion layer is connected with the first P-type buried layer; The first N+ region is arranged in a groove formed on the surface of the first P-type buried layer; the groove is formed above the N-type current expansion layer and the first P-type buried layer; The source polycrystalline silicon region, the grid polycrystalline silicon region and the oxide layer are arranged in the groove, and the oxide layer covers the surfaces of the source polycrystalline silicon region and the grid polycrystalline silicon region; the source electrode polycrystalline silicon region is connected with the first P-type buried layer, the first N+ region and the N-type current expansion layer through the oxidation layer, and a channel diode is formed below the source electrode polycrystalline silicon region through the N-type current expansion layer and the first P-type buried layer; The P-type base region is arranged above the N-type current expansion layer and is connected with the side face of the grid polycrystalline silicon region through the oxidation layer, and the barrier height formed by the N-type current expansion layer and the first P-type buried layer is smaller than the barrier height formed by the N-type current expansion layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer; the P+ region and the second N+ region are arranged above the P-type base region, the second N+ region is connected with the side face of the grid polycrystalline silicon region through the oxide layer, and the second N+ region and the P+ region are positioned on the same layer; the MOSFET device comprises a first P-type buried layer, a second P-type buried layer, a first N+ region, a second N+ region, a source electrode, a contact hole and a first P-type buried layer, wherein the source electrode is formed on the surfaces of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region and the second N+ region, the oxide layer corresponding to the source electrode polycrystalline silicon region is provided with the contact hole so that the source electrode is in contact with the source electrode polycrystalline silicon region, and the first P-type buried layer connected with the source electrode is used for reducing the electric field intensity at the bottom of a grid electrode groove when the MOSFET device is in a forward blocking state.
  2. 2. The MOSFET device of claim 1, wherein said N-type current spreading layer is L-type.
  3. 3. The MOSFET device of claim 1, wherein said oxide layer extends toward said second n+ region, covering a portion of a surface of said second n+ region.
  4. 4. The MOSFET device of claim 1, wherein said N-type substrate, said N-type epitaxial layer base material is silicon carbide.
  5. 5. The MOSFET device of claim 1, further comprising: the second P-type buried layer is arranged above the N-type substrate, the second P-type buried layer is connected with the N-type current expansion layer, the first P-type buried layer and the second P-type buried layer are respectively arranged on two sides of the N-type current expansion layer, the second P-type buried layer extends to the P+ region and is connected with the second N+ region, and the extension part of the second P-type buried layer is connected with the P-type base region.
  6. 6. The MOSFET device of claim 1, further comprising: And the drain electrode is arranged on the other side of the N+ type substrate.
  7. 7. The MOSFET device of claim 1, wherein said N-type current spreading layer has a doping concentration greater than said N-type epitaxial layer.
  8. 8. The MOSFET device of claim 1, wherein said N-type substrate is an n+ type substrate, said N-type epitaxial layer is an N-type epitaxial layer, and said N-type epitaxial layer has a doping concentration less than said N-type substrate.
  9. 9. The MOSFET device of claim 6, wherein said drain is a back metal layer and said source is a front metal layer.
  10. 10. A chip comprising a MOSFET device as claimed in any one of claims 1-9.

Description

MOSFET device and chip Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a MOSFET device and a chip. Background SiC MOSFETs (silicon carbide metal oxide semiconductor field effect transistors) are a type of high performance power semiconductor device based on silicon carbide (SiC) materials. However, when the MOSFET is in the reverse freewheel mode, i.e. the source voltage of the MOSFET is higher than the drain voltage, the body diode (parasitic diode) of the MOSFET is turned on, forming a reverse freewheel path, current flows from the source to the drain through the body diode of the MOSFET, the body diode of the SiC MOSFET has a high conduction voltage drop, resulting in a large conduction loss in the reverse freewheel mode, and minority carriers (holes) inside the device accumulate due to the conduction of the body diode, resulting in a phenomenon that the device performance is degraded. Disclosure of Invention In view of the above, embodiments of the present invention have been developed to provide a MOSFET device and chip that overcome, or at least partially solve, the above-described problems. To solve the above problems, an embodiment of the present invention discloses a MOSFET device, including: An N-type substrate; the N-type epitaxial layer is arranged on the other side of the N-type substrate; The N-type current expansion layer and the first P-type buried layer are arranged above the N-type epitaxial layer; the N-type current expansion layer is connected with the first P-type buried layer; The first N+ region is arranged in a groove formed on the surface of the first P-type buried layer; the groove is formed above the N-type current expansion layer and the first P-type buried layer; the source polycrystalline silicon region, the grid polycrystalline silicon region and the oxide layer are arranged in the groove, and the oxide layer covers the surfaces of the source polycrystalline silicon region and the grid polycrystalline silicon region; the source electrode polycrystalline silicon region is connected with the first P-type buried layer, the first N+ region and the N-type current expansion layer through the oxidation layer, the grid electrode polycrystalline silicon region is connected with the N-type current expansion layer through the oxidation layer, and the grid electrode polycrystalline silicon region is connected with the source electrode polycrystalline silicon region through the oxidation layer; The P-type base region is arranged above the N-type current expansion layer and is connected with the side face of the grid polycrystalline silicon region through the oxidation layer; the P+ region and the second N+ region are arranged above the P-type base region, the second N+ region is connected with the side face of the grid polycrystalline silicon region through the oxide layer, and the second N+ region and the P+ region are positioned on the same layer; The source electrode is formed on the surfaces of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region and the second N+ region, and contact holes are formed in the oxide layer corresponding to the source electrode polycrystalline silicon region so that the source electrode and the source electrode polycrystalline silicon region can be formed. Optionally, the N-type current expansion layer is L-type. Optionally, the oxide layer extends towards the second n+ region and covers a part of the surface of the second n+ region. Optionally, the barrier height formed by the N-type current expansion layer and the first P-type buried layer is smaller than the barrier height formed by the N-type current expansion layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer. Optionally, the substrate of the N-type substrate and the N-type epitaxial layer is silicon carbide. Optionally, the device further comprises a drain electrode arranged on one side of the N+ type substrate. Optionally, the doping concentration of the N-type current expansion layer is greater than that of the N-type epitaxial layer. Optionally, the N-type substrate is an n+ type substrate, the N-type epitaxial layer is an N-type epitaxial layer, and the doping concentration of the N-type epitaxial layer is smaller than that of the N-type substrate. Optionally, the drain electrode is a back metal layer, and the source electrode is a front metal layer. Accordingly, an embodiment of the present invention provides a chip including the MOSFET device described above. The embodiment of the invention has the following advantages: The MOSFET device comprises an N-type substrate, an N-type epitaxial layer, an N-type current expansion layer, a first P-type buried layer, a first N+ region, a groove, a P+ region, a second N+ region, a source polycrystalline silicon region, a grid polycrystalline silicon region and an oxide layer, wherein the N-t