CN-119943110-B - Memory device, control logic circuit and operation method thereof

Abstract

A memory device includes a memory array configured to store data and peripheral circuitry coupled to the memory array, the peripheral circuitry including control logic circuitry to control operation of the peripheral circuitry. The control logic circuit comprises a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact with each other through a first trigger signal and a first indication signal. The main control circuit and the first sub-control circuit interact through asynchronous control logic without a global clock signal.

Inventors

• SHENG YUE

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260512

Application Date

20231106

Claims (20)

1. 1. A memory device, comprising: a memory array configured to store data; Peripheral circuitry coupled to the memory array and including control logic circuitry to control operation of the peripheral circuitry, Wherein the control logic circuit comprises a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact with a first indication signal through a first trigger signal, Wherein the first sub-control circuit includes: An asynchronous control circuit configured to receive the first trigger signal from the main control circuit and generate a local clock signal, and A state machine circuit configured to receive the local clock signal and generate the first indication signal, wherein the state machine circuit includes at least one state triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a first output configured to output a next signal when the state is switched, and an indication output; A first exclusive-OR gate including a first input configured to receive the first trigger signal, a second input, and a second output coupled to the asynchronous control circuit, and A first delay element disposed between the second input of the first exclusive-or gate and the first output of the state machine circuit.
2. 2. The memory device of claim 1, wherein the main control circuit and the first sub-control circuit interact through asynchronous control logic without a global clock signal.
3. 3. The memory device of claim 1, wherein the asynchronous control circuit comprises: A second exclusive-or gate comprising a third input, a fourth input, and a third output, wherein the third input is configured to receive an output signal from the second output, and the third output is configured to output the local clock signal; A flip-flop circuit including an enable terminal coupled to the third output terminal of the second exclusive-OR gate, a fourth output terminal, and a data terminal coupled to the fourth output terminal, and And a second delay element disposed between the fourth input of the second exclusive-or gate and the fourth output of the flip-flop circuit.
4. 4. The memory device of claim 3, wherein the flip-flop circuit comprises a D flip-flop.
5. 5. The memory device of claim 3, wherein the asynchronous control circuit further comprises an inverter between the data terminal and the fourth output terminal of the flip-flop circuit.
6. 6. The memory device of claim 1, wherein the indication output is configured to output the first indication signal when switching the state in the state machine circuit.
7. 7. The memory device of claim 3, wherein the second output of the first exclusive-or gate is coupled to the third input of the second exclusive-or gate.
8. 8. The memory device of claim 3, wherein the first delay element comprises at least one inverter and the second delay element comprises at least one inverter.
9. 9. The memory device of claim 1, wherein the control logic circuit further comprises a second sub-control circuit, and the main control circuit and the second sub-control circuit interact with a second indication signal via a second trigger signal.
10. 10. The memory device of claim 9, wherein the first sub-control circuit and the second sub-control circuit are independently operable.
11. 11. The memory device of claim 10, wherein the main control circuit is configured to output the first trigger signal and the second trigger signal, respectively, and to receive the first indication signal and the second indication signal, respectively.
12. 12. A control logic circuit for controlling operation of peripheral circuits of a memory device, comprising: a main control circuit and at least one first sub-control circuit, the main control circuit and the at least one sub-control circuit interacting with each other through a first trigger signal and a first indication signal; wherein the sub-control circuit includes: an asynchronous control circuit configured to receive the first trigger signal and generate a local clock signal, and A state machine circuit configured to receive the local clock signal and generate the first indication signal, wherein the state machine circuit includes at least one state triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a first output configured to output a next signal when the state is switched, and an indication output; A first exclusive-OR gate including a first input configured to receive the first trigger signal, a second input, and a second output coupled to the asynchronous control circuit, and A first delay element disposed between the second input of the first exclusive-or gate and the first output of the state machine circuit.
13. 13. The control logic circuit of claim 12, wherein the asynchronous control circuit comprises: A second exclusive-or gate comprising a third input, a fourth input, and a third output, wherein the third input is configured to receive an output signal from the second output, and the third output is configured to output the local clock signal; A flip-flop circuit including an enable terminal coupled to the third output terminal of the second exclusive-OR gate, a fourth output terminal, and a data terminal coupled to the fourth output terminal, and And a second delay element disposed between the fourth input of the second exclusive-or gate and the fourth output of the flip-flop circuit.
14. 14. The control logic circuit of claim 13, wherein the flip-flop circuit comprises a D flip-flop.
15. 15. The control logic circuit of claim 13, wherein the asynchronous control circuit further comprises an inverter between the data terminal and the fourth output terminal of the flip-flop circuit.
16. 16. The control logic circuit of claim 12, wherein the indication output is configured to output the first indication signal when switching the state in the state machine circuit.
17. 17. The control logic circuit of claim 13, wherein the second output of the first exclusive-or gate is coupled to the third input of the second exclusive-or gate.
18. 18. The control logic of claim 13, wherein the first delay element comprises at least one inverter and the second delay element comprises at least one inverter.
19. 19. The control logic circuit of claim 12, further comprising a second sub-control circuit, wherein the main control circuit and the second sub-control circuit interact with a second indication signal via a second trigger signal.
20. 20. The control logic circuit of claim 19, wherein the first sub-control circuit and the second sub-control circuit are independently operable.

Description

Memory device, control logic circuit and operation method thereof Technical Field The present disclosure relates to memory devices, control logic circuits, and operations thereof. Background A memory device such as a flash memory is a low cost, high density, non-volatile solid state storage medium that can be electrically erased and reprogrammed. Peripheral circuits of a memory device typically include various register circuits and corresponding control logic circuits that interact with the main control digital circuits through global clock and bus protocols to complete the operation of the memory device. However, the wiring on these global clocks and buses is very long, consuming power on the clocks and buses. Disclosure of Invention In one aspect, a memory device is disclosed. The memory device includes a memory array configured to store data and peripheral circuitry coupled to the memory array, the peripheral circuitry including control logic circuitry to control operation of the peripheral circuitry. The control logic circuit comprises a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact with each other through a first trigger signal and a first indication signal. In some embodiments, the main control circuit and the first sub-control circuit interact through asynchronous control logic without a global clock signal. In some embodiments, the first sub-control circuit includes an asynchronous control circuit configured to receive the first trigger signal from the main control circuit and generate a local clock signal, and a state machine circuit configured to receive the local clock signal and generate the first indication signal. In some embodiments, the asynchronous control circuit includes a first exclusive-or gate including a first input configured to receive the first trigger signal and a second input configured to output the local clock signal, a flip-flop circuit including an enable terminal coupled to the first output terminal of the first exclusive-or gate, a second output terminal, and a data terminal coupled to the second output terminal, and a first delay element disposed between the second input terminal of the first exclusive-or gate and the second output terminal of the flip-flop circuit. In some embodiments, the flip-flop circuit comprises a D flip-flop. In some embodiments, the asynchronous control circuit further comprises an inverter between the data terminal and the second output terminal of the flip-flop circuit. In some embodiments, the state machine circuit includes at least one state triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a third output configured to output a next signal when the state is switched, and an indication output. In some embodiments, the indication output is configured to output the first indication signal when switching the state in the state machine circuit. In some embodiments, the memory device further includes a second exclusive-or gate including a third input configured to receive the first trigger signal, a fourth input, and a fourth output coupled to the asynchronous control circuit, and a second delay element disposed between the fourth input of the second exclusive-or gate and the third output of the state machine circuit. In some embodiments, the fourth output of the second exclusive-or gate is coupled to the first input of the first exclusive-or gate. In some embodiments, the first delay element comprises at least one inverter and the second delay element comprises at least one inverter. In some embodiments, the control logic circuit further comprises a second sub-control circuit, and the main control circuit and the second sub-control circuit interact with a second indication signal via a second trigger signal. In some embodiments, the first sub-control circuit and the second sub-control circuit are independently operated. In some embodiments, the main control circuit is configured to output the first trigger signal and the second trigger signal, respectively, and to receive the first indication signal and the second indication signal, respectively. In another aspect, a control logic circuit for controlling operation of peripheral circuits of a memory device is disclosed. The control logic circuit comprises a main control circuit and at least one first sub-control circuit, wherein the main control circuit and the at least one first sub-control circuit interact with each other through a first trigger signal and a first indication signal. The sub-control circuit includes an asynchronous control circuit configured to receive the first trigger signal and generate a local clock signal, and a state machine circuit configured to receive the local clock signal and generate a first indication signal. In some embodiments, the asynchronous control circuit includes a fir