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CN-119943121-B - Flash memory testing method

CN119943121BCN 119943121 BCN119943121 BCN 119943121BCN-119943121-B

Abstract

The invention provides a test method of a flash memory, which comprises the steps of after all storage units of the flash memory are erased to be 1, adding voltage to carry out floating gate defect screening, wherein the voltage difference between a source area and a bit line added on the storage units is far greater than the voltage difference between the source area and the bit line in an operation mode of a terminal user through the test method, the source area voltage is coupled to the floating gate, and the storage units are overlapped with positive potentials of the storage units after being erased, so that the floating gate defect screening is far greater than the voltage difference between the floating gate and the bit line in the operation mode of the terminal user, abnormal floating gates and the bit line of the storage units are in breakdown interconnection, writing 1 operation is carried out on the flash memory, writing 1 failure is carried out on the storage units in an entire column where the abnormal floating gates are located, and therefore the storage units in the entire column where the abnormal floating gates are located are screened out. And the floating gate defect chip is screened out in a yield test stage and does not flow to a terminal user, so that the reliability risk of terminal failure is reduced. The reliability of the flash memory is improved, and the use failure of the flash memory terminal user mode is avoided.

Inventors

  • XIE ZHONGHUA
  • TANG XIAN

Assignees

  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260508
Application Date
20250106

Claims (10)

  1. 1. A method for testing a flash memory, comprising: Providing a flash memory, wherein the flash memory comprises a storage unit array, wherein the storage unit array comprises a plurality of storage units which are arranged in a matrix, and the storage units are split gate type flash memory units, each storage unit comprises a floating gate, a word line and a bit line which are all positioned on a substrate, and the storage units of each column share the bit line; Erasing the storage unit of the flash memory; performing voltage-added floating gate defect screening on the erased memory cell to puncture and interconnect the abnormal floating gate of the memory cell and the bit line, wherein the voltage difference between a source region and the bit line, which are added on the memory cell, of the floating gate defect screening is higher than that which is added on the source region and the bit line when a terminal user actually uses the memory cell; The method comprises the steps of performing a writing operation of '1' on the flash memory, wherein the writing operation of '1' on the storage units of the whole column where the abnormal floating gate is located is invalid, so that the storage units of the whole column where the abnormal floating gate is located are screened out, the writing operation of '1' is to maintain that the storage bit of the storage unit is always in a '1' state after erasure, voltages are applied to a plurality of storage units which do not need programming, so that the storage unit does not meet the programming condition, the voltage of a channel is not opened, electrons of the corresponding storage unit cannot enter the floating gate from the substrate, and the storage bit of the storage unit is always in a '1' state.
  2. 2. The method for testing a flash memory according to claim 1, wherein, And screening the voltage difference between the source region and the bit line, which is added to the storage unit, by the floating gate defect, wherein the voltage difference is 8.6V-9.4V.
  3. 3. The method for testing a flash memory according to claim 2, wherein, In the floating gate defect screening, the voltage test conditions applied to the memory cell further comprise the range of the source region voltage V S is 8.6V-9.4V, the range of the bit line voltage V B is 0V-1V, and the range of the word line voltage V W is 0V-2V.
  4. 4. The method for testing a flash memory according to claim 1, wherein, After providing the flash memory, the method further comprises the following steps before erasing the flash memory: And the first test comprises short circuit, open circuit and electric leakage tests, wherein the first test flows into the second test if the first test is qualified, and the first test is rejected if the first test is unqualified.
  5. 5. The method for testing a flash memory according to claim 4, wherein, The second test comprises the steps of performing static power consumption and dynamic power consumption tests, flowing into the erasing step if the second test is qualified, and rejecting if the second test is unqualified.
  6. 6. The method for testing a flash memory according to claim 3, The write "1" operation plus voltage condition includes the source voltage V S being 8.2V, the bit line voltage V B being 2.5V, and the word line voltage V W being 1.6V.
  7. 7. The method for testing a flash memory according to claim 1, wherein, After erasing the flash memory, before the floating gate defect screening, the method further comprises: And performing read operation on the erased memory cell, judging whether the erased memory bit is in a1 state according to the read current, if the erased memory bit is in the 1 state, successfully performing the floating gate defect screening by erasing, and if the erased memory bit is not in the 1 state, failing to erase the memory cell and rejecting the memory cell.
  8. 8. The method for testing flash memory as recited in claim 7, wherein, After the writing of the 1 operation is performed on the flash memory, the method further comprises the steps of performing a reading operation on the memory unit after the writing of the 1 operation, judging whether the memory bit maintains the 1 state after the writing of the 1 according to the read current, if the memory bit maintains the 1 state, successfully writing the 1 operation, and if the memory bit maintains the 0 state, failed writing the 1 operation, and eliminating.
  9. 9. The method for testing a flash memory according to claim 1, wherein, The split gate type flash memory unit comprises two storage structures which share a source region and are symmetrically distributed, wherein the storage structures comprise a drain region and a source region which are positioned in a substrate, the drain region is connected with a bit line, a floating gate and a word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on one side, close to the word line, of the floating gate, and a tunneling oxide layer is formed between the floating gate and the word line.
  10. 10. The method for testing flash memory as recited in claim 9, wherein, The abnormal floating gate includes a case where the floating gate tip which is supposed to be formed on the side of the floating gate close to the word line is not formed.

Description

Flash memory testing method Technical Field The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a method for testing a flash memory. Background Flash memory is widely used in electronic products such as portable computers, mobile phones, digital music players, etc. as an integrated circuit memory device has an electrically erasable function for storing information and the stored information is not lost after power is turned off. As shown in fig. 1, in a split gate flash memory, some memory cells may have abnormal morphology due to process environment defects during the process. The memory structure to the left of the trench 030 includes a first floating gate 011 and a first word line 012, and the memory structure to the right of the trench 030 includes a second floating gate 021 and a second word line 022. The first floating gate 011 is of a normal morphology, the position of the first floating gate 011 facing the first word line 012 has a sharp corner, and a gap is formed between the first floating gate 011 and the first word line 012. Bit lines are formed in the trenches 030. The second floating gate 021 (inside the yellow ellipse) has an abnormal shape, and the position of the second floating gate 021 facing the second word line 022 is not formed into a sharp corner shape which is supposed to be present, and the left side position of the second floating gate 021 inside the yellow ellipse in fig. 1 is also longer than the left side position. In general, such defective memory cells are screened out and repaired by the punch-through crosstalk test item during the yield test process, and can be shipped and used normally. Although the defective memory cell is repaired in the yield test, other rows in the memory array share the bit line with the defective memory cell and are not completely independent. Although shipped as a normal sample, the defective memory cell bit line is subject to leakage during continued use by the end user due to the different defect morphology, resulting in failure of the entire row of memory cells during the write "1" operation, and thus a terminal failure event. Disclosure of Invention The invention aims to provide a test method of a flash memory, which is characterized in that after all storage units of the flash memory are erased to be 1, a voltage floating gate defect screening is performed to puncture and interconnect abnormal floating gates and bit lines of the storage units, so that when the flash memory is subjected to a1 writing operation, the storage units of the whole columns where the abnormal floating gates are located are invalid in a1 writing operation, and the storage units of the whole columns where the abnormal floating gates are located are screened out. And the floating gate defect chip is screened out in a yield test stage and does not flow to a terminal user, so that the reliability risk of terminal failure is reduced. The reliability of the flash memory is improved, and the use failure of the flash memory terminal user mode is avoided. The invention provides a method for testing a flash memory, which comprises the following steps: providing a flash memory, wherein the flash memory comprises a storage unit array, wherein the storage unit array comprises a plurality of storage units which are arranged in a matrix, and the storage units are split gate type flash memory units, each storage unit comprises a floating gate and a bit line, and the bit line is shared by the storage units of each column; Erasing the storage unit of the flash memory; The method comprises the steps of performing voltage floating gate defect screening on an erased memory cell to puncture and interconnect an abnormal floating gate of the memory cell with a bit line, wherein the voltage difference between a source region and the bit line, which are applied to the memory cell, of the floating gate screening is higher than that of the source region and the bit line when a terminal user actually uses the floating gate screening; and performing a writing "1" operation on the flash memory, wherein writing "1" of the storage units of the whole column where the abnormal floating gate is located is invalid, so that the storage units of the whole column where the abnormal floating gate is located are screened out. Further, the floating gate defect screening is performed on the voltage difference between the source region and the bit line of the storage unit, wherein the voltage difference is 8.6V-9.4V. Further, in the floating gate defect screening, the voltage test conditions applied to the memory cell further include a range of 8.6V-9.4V of the source voltage V S, a range of 0V-1V of the bit line voltage V B, and a range of 0V-2V of the word line voltage V W. Further, after the flash memory is provided, before the flash memory is erased, the method further comprises: And the first test comprises short circuit, open circuit and electric leakag