CN-119947109-B - Memory, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the application provides a memory, a manufacturing method thereof and electronic equipment. The memory includes a substrate and a plurality of memory cells including a transistor including a gate electrode, a gate insulating layer, a channel region, and two first protection structures. The gate insulating layer and the channel region are sequentially arranged on the periphery of the gate electrode, the gate insulating layer and the gate electrode extend along a first direction perpendicular to the substrate, the first protection structure is arranged on at least one side of the channel region along a second direction, the second direction is parallel to the substrate, and the etching rate of the material of the channel region is larger than that of the material of the first protection structure. The channel region and the first protection structure can form a relatively obvious etching selection ratio, and the first protection structure can protect the channel region when the parasitic channel region is etched, so that the performance stability of the memory is improved.

Inventors

• LI WEIRAN
• JIA LIBIN
• WANG NAIZHENG
• PING YANLEI
• DONG SHUCHENG

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20231101

Claims (16)

1. 1. A memory is characterized by comprising a substrate and a plurality of memory cells, wherein the memory cells comprise transistors and a capacitor structure, and the transistors comprise: The semiconductor device comprises a substrate, a gate electrode, a gate insulating layer and a channel region, wherein the gate insulating layer and the channel region are sequentially arranged on the periphery of the gate electrode; the first protection structure is arranged on at least one side of the channel region along a second direction, and the second direction is parallel to the substrate; a source electrode; The capacitor structure comprises a second electrode layer, a capacitor insulating layer, a first electrode layer and a series structure, wherein the second electrode layer is sequentially arranged on one side of the source electrode; The capacitor insulating layer wraps the two opposite sides of the second electrode layer along the first direction and the two opposite sides of the second direction, and the first electrode layer and the series structure cover the capacitor insulating layer along the shape in sequence.
2. 2. The memory of claim 1, wherein the material of the channel region comprises a metal oxide and the material of the first guard structure comprises a nitride.
3. 3. The memory of claim 1 wherein the transistor further comprises a drain, the source and the drain being disposed on opposite sides of the channel region along a third direction, respectively, the third direction being parallel to the substrate and intersecting the second direction.
4. 4. The memory of claim 3, wherein in a cross-section parallel to both the first direction and the second direction, the channel region is in contact with the first guard structure along at least one side of the second direction; And/or, in a section parallel to both the first direction and the third direction, the channel region contacts the source and the drain, respectively, along both sides of the third direction.
5. 5. The memory of claim 4 wherein the first guard structure has a bottom surface proximate to the substrate and a top surface distal from the substrate, and a side surface between the top surface and the bottom surface, the channel region being in contact with the top surface, the bottom surface, and the side surface of the first guard structure.
6. 6. A memory according to claim 3, wherein a plurality of said transistors are stacked in a first direction perpendicular to the substrate, arranged in an array in a plane parallel to the substrate; The drain of the transistor has a bottom surface proximate to the substrate and a top surface distal from the substrate, and a side surface between the top surface and the bottom surface, the channel region being in contact with the top surface, the bottom surface, and the side surface of the drain.
7. 7. The memory of claim 6, wherein gate electrodes of two adjacent transistors are connected by a connection line along the first direction to form a word line.
8. 8. The memory of claim 7, wherein a width of the connection line is greater than a width of the gate electrode in the second direction.
9. 9. The memory of claim 6, wherein a bit line is disposed between a drain of one of the transistors and a drain of the other of the transistors in a third direction, the bit line extending in the second direction.
10. 10. An electronic device comprising a memory as claimed in any one of claims 1-9.
11. 11. A method of manufacturing a memory, comprising: Manufacturing a plurality of first storage structures arranged in an array in an insulating manner on one side of a substrate, wherein the first storage structures comprise a plurality of first grooves arranged in an array in a plane parallel to the substrate, a plurality of first sacrificial structures arranged around the periphery of the first grooves at intervals along a first direction perpendicular to the substrate, and a first protection structure arranged on at least one side of the first grooves along a second direction, and the second direction is parallel to the substrate; Laterally etching the first sacrificial structure through the first groove, removing part of the first sacrificial structure, forming a second sacrificial structure, and forming a second groove by the first groove; Sequentially manufacturing a semiconductor layer, a gate insulating layer and a word line in the second groove along with the shape; And taking the first protection structure as a mask, removing the exposed semiconductor layer, and forming a channel region by the rest semiconductor layer, wherein the etching rate of the material of the channel region is greater than that of the material of the first protection structure.
12. 12. The method of manufacturing according to claim 11, further comprising, before manufacturing the plurality of phase-insulated first memory structures arranged in an array on one side of the substrate: Manufacturing a first insulating layer and a replacement layer alternately arranged on one side of a substrate; Patterning each first insulating layer and each replacement layer to form a plurality of first word line grooves arrayed in a plane parallel to the substrate; laterally etching each first insulating layer through the first word line grooves to obtain second word line grooves formed by the first word line grooves; a sacrificial word line is fabricated within the second word line trench.
13. 13. The method of manufacturing of claim 12, further comprising, after fabricating the sacrificial word line in the second word line trench and before fabricating the first memory structure of the plurality of phase-insulated array arrangements on one side of the substrate: patterning the first insulating layer and the replacement layer to form first storage structure areas arranged in an array manner, and obtaining first isolation grooves between adjacent first storage structure areas; And manufacturing a first isolation layer in the second isolation groove to obtain an initial first storage structure of array arrangement which is insulated with each other.
14. 14. The method of manufacturing according to claim 13, wherein manufacturing a plurality of phase-insulated first memory structures arranged in an array on one side of a substrate, comprises: Removing the first insulating layer and the replacement layer which are positioned between any two adjacent sacrificial word lines in the same column along the second direction and extend along a third direction to form a replacement groove, wherein the third direction is parallel to the substrate and is intersected with the second direction; laterally removing the replacement layer through the replacement groove, and manufacturing an area filled with the replacement layer and an initial metal layer of the replacement groove; Removing part of the initial metal layer extending along the third direction between any two adjacent sacrificial word lines in the same column along the second direction to form a transition metal layer and a third groove; Manufacturing a second isolation layer along the third groove along with the shape; patterning the sacrificial word line to obtain a third word line groove with the same size as the first word line groove; The transition metal layer is laterally etched through the third word line groove to remove the transition metal layers located on two sides of the third word line groove along the second direction, so that a fourth word line groove formed by the third word line groove and a metal layer obtained by the transition metal layer are obtained, wherein the metal layer comprises bit lines located between two adjacent rows of sacrificial word lines along the third direction and extending along the second direction, drain electrodes arranged on one side of the sacrificial word lines and connected with the bit lines, and source electrodes located on the other side of the sacrificial word lines; manufacturing a third isolation layer in the fourth word line groove; And patterning the third isolation layer to obtain the first groove and the first protection structure, wherein the width of the first groove along the second direction is equal to the width of the third word line groove.
15. 15. The method of manufacturing of claim 14, wherein laterally etching the transition metal layer through the third word line trench to remove the transition metal layer located on both sides of the third word line trench in the second direction, resulting in a fourth word line trench formed from the third word line trench, comprises: Removing part of the transition metal layers positioned on two sides of the third word line groove along the third direction, so that a second width is formed by the first width along the width between two adjacent transition metal layers along the third direction; Patterning the third isolation layer to obtain the first groove and the first protection structure with the width along the second direction being equal to the width of the third word line groove, wherein the patterning comprises the following steps: and patterning the third isolation layer to obtain the first groove with the width of the second width along the third direction.
16. 16. The method of manufacturing of claim 14, further comprising, after the second insulating layer is manufactured in the third trench, before patterning the sacrificial word line: Removing the first insulating layer, the second insulating layer and the second isolating layer of the capacitor region to expose the transition metal layer in the capacitor region to form a capacitor trench; Sequentially manufacturing a capacitor insulating layer, a first electrode layer and a series structure on the periphery of the exposed transition metal layer and along the capacitor groove; The series structure of the transistor region is removed.

Description

Memory, manufacturing method thereof and electronic equipment Technical Field The application relates to the technical field of semiconductors, in particular to a memory, a manufacturing method thereof and electronic equipment. Background In the current memories, the memory density requirements are continuously increasing. In order to improve the integration capability, the cell area is reduced, more memory cells are manufactured in the same area of the chip, and the memory cell size is required to be continuously reduced along with the development of technology. As memory density increases and individual memory cell sizes decrease, more problems are also prone to occur. Disclosure of Invention The application provides a memory, a manufacturing method thereof and electronic equipment. In a first aspect, some embodiments of the present application provide a memory comprising a substrate and a plurality of memory cells, the memory cells comprising transistors comprising: The semiconductor device comprises a substrate, a gate electrode, a gate insulating layer and a channel region, wherein the gate insulating layer and the channel region are sequentially arranged on the periphery of the gate electrode; The first protection structure is arranged on at least one side of the channel region along a second direction, the second direction is parallel to the substrate, and the etching rate of the material of the channel region is larger than that of the material of the first protection structure. In a second aspect, some embodiments of the present application provide an electronic device comprising the memory of the first aspect. In a third aspect, some embodiments of the present application provide a method for manufacturing a memory, including: manufacturing a plurality of first storage structures arranged in an array manner in an insulating manner on one side of a substrate, wherein the first storage structures comprise a plurality of first grooves arranged in an array manner in a plane parallel to the substrate, a plurality of first sacrificial layers which are arranged around the periphery of the first grooves at intervals along a first direction perpendicular to the substrate, and first protection structures arranged on at least one side of the first grooves along a second direction, and the second direction is parallel to the substrate; Laterally etching the first sacrificial structure through the first groove, removing part of the first sacrificial structure, forming a second sacrificial structure, and forming a second groove by the first groove; Sequentially manufacturing a semiconductor layer, a gate insulating layer and a word line in the second groove along with the shape, wherein the word line fills the second groove; And taking the first protection structure as a mask, removing the exposed semiconductor layer, and forming a channel region by the rest semiconductor layer, wherein the etching rate of the material of the channel region is greater than that of the material of the first protection structure. The technical scheme provided by the embodiments of the application has the following beneficial technical effects: The etching rate of the material of the first protection structure outside the channel region is smaller than that of the material of the channel region, so that a relatively obvious etching selection ratio can be formed between the channel region and the first protection structure, and the channel region can be protected when the semiconductor layer connected with the channel region is removed. For the memory for manufacturing the laminated layer, the channel region is protected by the first protection structure, so that the channel region is prevented from being damaged due to the fact that the etching rate of the top and the bottom is different due to the fact that the etching agent concentration from the top to the bottom is reduced, namely, even if the etching agent concentration at the bottom of the groove is smaller than that at the top, the parasitic channel region of the parasitic transistor at the bottom is removed by etching by the etching agent at the bottom, the channel regions of the (non-parasitic) transistors at other positions are still covered by the first protection structure and are not damaged by etching by the etching agent, the structural integrity of the transistors is improved, the structural stability of the laminated layer memory is improved, the removal rate of the channel region of the parasitic transistor is improved, the influence of the parasitic transistor is reduced, and the performance of the transistor is guaranteed or improved. Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Drawings FIG. 1 is a schematic cross-sectional view of a memory device parallel to a first direction and a third direct