CN-119947207-B - Split gate SiC MOSFET device and preparation method thereof

CN119947207BCN 119947207 BCN119947207 BCN 119947207BCN-119947207-B

Abstract

The invention discloses a split gate SiC MOSFET device and a preparation method thereof, relating to the technical field of semiconductors, comprising a plurality of cell structures arranged in an array; the cell structure comprises a body region arranged in an epitaxial layer, an N+ source region is arranged in the middle of the body region, a P+ region is arranged in the middle of the N+ source region, part of the upper surface of the body region, part of the upper surface of the N+ source region and the upper surface of the P+ region are exposed, an N+ region is arranged between adjacent cell structures, a stepped P region is arranged on the upper surface of the N+ region, or an N+ region is arranged between diagonal cell structures, and a stepped P region is arranged on the upper surface of the N+ region. The invention can improve the performance of the SiC MOSFET device.

Inventors

JIA RENXU
XU ZEYU
YUAN LEI
ZHANG YUMING

Assignees

西安电子科技大学

Dates

Publication Date: 20260512
Application Date: 20250116

Claims (8)

1. The isolated gate SiC MOSFET device is characterized by comprising a plurality of cell structures arranged in an array, wherein each cell structure comprises a body region arranged in an epitaxial layer, an N+ source region is arranged in the middle of the body region, and a P+ region is arranged in the middle of the N+ source region, wherein part of the upper surface of the body region, part of the upper surface of the N+ source region and the upper surface of the P+ region are exposed; An N+ region is arranged between adjacent cell structures, and a stepped P region is arranged on the upper surface of the N+ region; And/or an N+ region is arranged between the opposite corner cell structures, and a stepped P region is arranged on the upper surface of the N+ region; The step-shaped P region comprises a first P region and a second P region, the first P region is positioned on the upper surface of the N+ region, the second P region is positioned on two sides of the first P region along the direction parallel to the epitaxial layer and along the direction perpendicular to the epitaxial layer, the orthographic projection of the first P region is overlapped with the orthographic projection of the N+ region, and the orthographic projection of the second P region is not overlapped with the orthographic projection of the N+ region; And along the direction perpendicular to the epitaxial layer, the height of the first P region is larger than that of the second P region, and the doping concentration of the first P region is smaller than that of the second P region.
2. The split gate SiC MOSFET device of claim 1, further comprising a gate dielectric layer disposed on an upper surface of the epitaxial layer and overlying an exposed upper surface of the body region and in contact with a portion of an upper surface of the exposed N+ source region and in contact with a portion of an upper surface of the stepped P region; the grid electrode is arranged on the upper surface of the grid dielectric layer, and the orthographic projection of the grid electrode is overlapped with the orthographic projection of the grid dielectric layer along the direction perpendicular to the epitaxial layer.
3. The split-gate SiC MOSFET device of claim 2, wherein the orthographic projections of the gates are ring-shaped structures in a direction perpendicular to the epitaxial layer, and orthographic projections of adjacent gates overlap orthographic projections of the same stepped P-region.
4. The split gate SiC MOSFET device of claim 1, wherein the first P region has a doping concentration of 1e 16-1 e20cm 2 and the second P region has a doping concentration of 1e 16-1 e18cm 2 .
5. The split gate SiC MOSFET device of claim 1, wherein the orthographic projection of the stepped P-region is in a grid shape disposed between adjacent ones of the cell structures and between diagonal ones of the cell structures in a direction perpendicular to the epitaxial layer.
6. The split gate SiC MOSFET device of claim 1, wherein the orthographic projection of the stepped P-region is in the form of a discontinuous stripe disposed between adjacent ones of the cell structures in a direction perpendicular to the epitaxial layer.
7. The split gate SiC MOSFET device of claim 1, wherein the orthographic projection of the stepped P-region is punctiform in a direction perpendicular to the epitaxial layer, disposed between diagonally opposite cell structures.
8. A method for manufacturing a split gate SiC MOSFET device according to any one of claims 1 to 7, comprising: Providing an epitaxial layer; forming a plurality of body regions arranged in an array in the epitaxial layer by means of ion implantation; forming an N+ source region in the middle region of the body region by means of ion implantation; Forming a P+ region in the middle region of the N+ source region by means of ion implantation; forming an N+ region between adjacent body regions by means of ion implantation, and forming a stepped P region in the N+ region by means of ion implantation; And/or forming an N+ region between the diagonal body regions by means of ion implantation, and forming a stepped P region in the N+ region by means of ion implantation.

Description

Split gate SiC MOSFET device and preparation method thereof Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to a split gate SiC MOSFET device and a preparation method thereof. Background The SiC material is used as a typical representative of a third-generation semiconductor material, has the advantages of wide forbidden band, high heat conductivity, high critical electric field, higher electron mobility and the like, and the manufactured device is one of the devices with the most development prospects at present, has the characteristics of low impedance, high voltage, high temperature, high frequency, high efficiency, radiation resistance and the like, and is widely applied to the fields of automobile electronics, photovoltaic inversion, energy storage, aerospace and the like. The SiC devices mainly comprise three series of SiC SBDs, siC MOSFETs and SiC IGBTs, and the market is mainly developed by the SiC SBDs and the SiC MOSFETs at present. In SiC MOSFET field effect transistors, breakdown typically occurs at the edge curvature, i.e., the PN junction corner curvature, where the area covered by the gate oxide layer is at its maximum electric field strength when the MOSFET is in operation. In the existing design of a part of split gate device, the original grid electrode as a whole is divided into a left part and a right part so as to reduce the overlapping area of the grid electrode and a drain electrode, and on the premise of not reducing on-resistance, the charge capacitance at the grid oxide position is reduced, the dynamic and short-circuit performance is improved, and the design of the split gate reduces the grid capacitance and the grid charge, but the split gate SiC MOSFET exposes the edge of the grid electrode (Poly-Si), and a high electric field is generated by a grid oxide layer under the blocking characteristic. Accordingly, there is a need to provide a split gate SiC MOSFET device that ameliorates the deficiencies in the prior art. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a split gate SiC MOSFET device and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme: in a first aspect, the present invention provides a split gate SiC MOSFET device comprising: The cell structure comprises a body region arranged in an epitaxial layer, wherein an N+ source region is arranged in the middle of the body region, and a P+ region is arranged in the middle of the N+ source region, wherein part of the upper surface of the body region, part of the upper surface of the N+ source region and the upper surface of the P+ region are exposed; an N+ region is arranged between adjacent cell structures, and a stepped P region is arranged on the upper surface of the N+ region; and/or an N+ region is arranged between the diagonal cell structures, and a stepped P region is arranged on the upper surface of the N+ region. In a second aspect, the present invention further provides a method for preparing a split gate SiC MOSFET device, which is used for preparing the split gate SiC MOSFET device provided above, including: Providing an epitaxial layer; Forming a plurality of body regions arranged in an array in the epitaxial layer by means of ion implantation; forming an N+ source region in the middle region of the body region by means of ion implantation; Forming a P+ region in the middle region of the N+ source region by means of ion implantation; forming an N+ region between adjacent body regions by means of ion implantation, and forming a stepped P region in the N+ region by means of ion implantation; And/or forming an N+ region between the diagonal body regions by means of ion implantation, and forming a stepped P region in the N+ region by means of ion implantation. The invention has the beneficial effects that: The invention provides a split gate SiC MOSFET device and a preparation method thereof, the split gate SiC MOSFET device comprises an epitaxial layer, cell structures arranged in an array are arranged in the epitaxial layer, the cell structures comprise a body region, an N+ source region is arranged in the middle of the body region, a P+ region is arranged in the middle of the N+ source region, the P+ region penetrates through the whole N+ source region along the direction perpendicular to the epitaxial layer, the whole upper surface of the P+ region is exposed, the upper surface of a side surface region of the N+ source region is exposed, the upper surface of a side surface region of the body region is exposed, further, an N+ region is arranged between adjacent cell structures, a stepped P region is arranged on the upper surface of the N+ region, the N+ region and the stepped P region are arranged in the epitaxial layer, the upper surface of the stepped P region is arranged on the upper surface of the N+ region, the N+ region and th